Computer Architecture Techniques for Power-EfficiencyMorgan & Claypool Publishers, 2008. gada 8. sept. - 207 lappuses In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions |
Saturs
Modeling Simulation and Measurement | 9 |
Using Voltage and Frequency Adjustments to Manage Dynamic Power | 23 |
Optimizing Capacitance and Switching Activity to Reduce Dynamic Power | 45 |
Managing Static Leakage Power | 131 |
Conclusions | 181 |
Glossary | 187 |
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Adapted approach architectural techniques behavior benchmarks bit-line segmentation bits Bloom filters branch predictors buffer byte cache decay cache line capacitance chip circuit clock gating clock-gated CMOS compression configuration core counters cycles DATA DATA DATA decay interval decay-induced misses direct-mapped disabled domino logic drowsy mode DVFS dynamic power dynamic voltage scaling encoding execution Figure frequency frequent value functional units G DATA gated-V dd global hardware idle IEEE implementation increase inputs instruction cache instruction queue latches latency leakage power logic loop memoization microarchitecture misprediction miss rate narrow-width ofthe operands operation optimizations partition performance phase pipeline power consumption power dissipation power savings prediction processor proposed reduce resizing scaling scheme Section set-associative cache significant slack speculative execution SRAM structures subthreshold leakage superscalar supply voltage switching activity temperature thermal threshold voltage transistor wire wordlines