Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical InstituteSpringer Science & Business Media, 2008. gada 6. jūn. - 436 lappuses Verilog and its usage has come a long way since its original invention in the mid-80s by Phil Moorby. At the time the average design size was around ten thousand gates, and simulation to validate the design was its primary usage. But between then and now designs have increased dramatically in size, and automatic logic synthesis from RTL has become the standard design ?ow for most design. Indeed, the language has evolved and been re-standardized too. Overtheyears,manybookshavebeenwrittenaboutVerilog.Myown,coauthored with Phil Moorby, had the goal of de?ning the language and its usage, providing - amples along the way. It has been updated with ?ve new editions as the language and its usage evolved. However this new book takes a very different and unique view; that of the designer. John Michael Williams has a long history of working and teaching in the ?eld of IC and ASIC design. He brings an indepth presentation of Verilog and how to use it with logic synthesis tools; no other Verilog book has dealt with this topic as deeply as he has. If you need to learn Verilog and get up to speed quickly to use it for synthesis, this book is for you. It is sectioned around a set of lessons including presentation and explanation of new concepts and approaches to design, along with lab sessions. |
Saturs
| 21 | |
Week 2 Class 1 | 43 |
Week 2 Class 2 | 60 |
Week 3 Class 1 | 83 |
Week 3 Class 2 101 | 100 |
Week 4 Class 1 | 113 |
Week 4 Class 2 | 145 |
Week 5 Class 1 | 169 |
Week 8 Class 1 | 259 |
Week 8 Class 2 | 279 |
Week 9 Class 1 295 | 294 |
Week 9 Class 2 | 311 |
Week 10 Class 1 | 337 |
Week 10 Class 2 | 361 |
Week 11 Class 1 | 375 |
Week 11 Class 2 | 405 |
Week 5 Class 2 | 185 |
Week 6 Class 1 | 195 |
Week 6 Class 2 | 211 |
Week 7 Class 1 | 231 |
Week 7 Class 2 | 243 |
Week 12 Class 1 | 413 |
Week 12 Class 2 | 421 |
Index | 429 |
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Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical ... John Williams Priekšskatījums nav pieejams - 2008 |
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AdjustFreq allowed asserted assignment statement back-annotation begin blocking assignments buffer byte chip clock domain ClockIn combinational logic compile component concurrent connect continuous assignment copy count counter declared decoder default delay value DesDecoder Deserializer edge endmodule error event control example FIFO flip-flop format frequency FullDup functionality gate hardware hierarchy implemented initial block input instance instantiated integer keyword latch localparam loop memory module header module named negedge netlist NextState nonblocking assignments operator Optional output port Palnitkar parallel parameter parity parity bit ParValid PCI Express QReg rename Reset scan chain schematic sequential sequential logic SerDes serial clock serial data setup shift register shown in Fig specify block specparam Springer Science+Business Media Step subdirectory synchronization synthesized netlist synthesizer System Verilog task testbench Thomas and Moorby trireg TSMC variable vector VLSI width wire
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