Embedded Software and Systems: Second International Conference, ICESS 2005, Xi'an, China, December 16-18, 2005, ProceedingsLaurence T. Yang, Xingshe Zhou, Wei Zhao, Zhaohui Wu, Yian Zhu, Man Lin Springer, 2005. gada 30. nov. - 784 lappuses Welcome to the proceedings of the 2005 International Conference on Emb- ded Software and Systems (ICESS 2005) held in Xian, China, December 16-18, 2005. With the advent of VLSI system level integration and system-on-chip, the center of gravity of the computer industry is now moving from personal c- puting into embedded computing. Embedded software and systems are incre- ingly becoming a key technological component of all kinds of complex technical systems, ranging from vehicles, telephones, aircraft, toys, security systems, to medical diagnostics, weapons, pacemakers, climate control systems, etc. The ICESS 2005 conference provided a premier international forum for - searchers, developers and providers from academia and industry to address all resulting profound challenges; to present and discuss their new ideas, - search results, applications and experience; to improve international com- nication and cooperation; and to promote embedded software and system - dustrialization and wide applications on all aspects of embedded software and systems. |
Saturs
1 | |
16 | |
30 | |
50 | |
Ahead of Time Deployment in ROM of a JavaOS | 63 |
A Packet PropertyBased Task Scheduling Policy for Control Plane | 85 |
Component Development Platform for Communication Protocols | 107 |
Separate Compilation for Synchronous Modules | 129 |
A Compiler Infrastructure for Java Reconfigurable Computing | 386 |
CCD CameraBased Range Sensing with FPGA for RealTime | 398 |
Agent and Distributed Computing | 408 |
Data Storage in Sensor Networks for Multidimensional Range Queries | 420 |
Wireless Communications | 441 |
PowerEfficient Packet Scheduling Method for IEEE 802 15 3 WPAN | 462 |
On LocationFree Node Scheduling Scheme for Random Wireless | 484 |
The Study and Implementation of Wireless Network Router NPU1 | 506 |
RealTime Systems | 150 |
Elimination of Nondeterministic Delays in a RealTime Database | 172 |
Solving RealTime Scheduling Problems with ModelChecking | 186 |
PowerAware Computing | 210 |
CompilerDirected EnergyAware Prefetching Optimization | 230 |
A Dynamic Energy Conservation Scheme for Clusters in Computing | 244 |
Network on Chip for Parallel DSP Architectures | 265 |
Designing OnChip Network Based on Optimal Latency Criteria | 287 |
Testing and Verification | 299 |
Selfcorrection of FPGABased Control Units | 310 |
Detecting Memory Access Errors with FlowSensitive Conditional | 320 |
Deductive Probabilistic Verification Methods of Safety Liveness | 332 |
Specification and Verification Techniques of Embedded Systems Using | 346 |
Formalization of fFSM Model and Its Verification | 361 |
Reconfigurable Computing | 373 |
Hierarchical Route Optimization in Mobile Network and Performance | 522 |
A CoverageAware Reader Collision | 542 |
Multimedia and HumanComputer Interaction | 564 |
RealTime Expression Mapping with Ratio Image | 586 |
Network Protocol Security and FaultTolerance | 608 |
An Improvement on StrongPassword Authentication Protocols | 629 |
A RevenueAware Bandwidth Allocation Model and Algorithm in | 650 |
Support Industrial Hard RealTime Traffic with Switched Ethernet | 671 |
Localized EnergyAware Broadcast Protocol for Wireless Networks | 696 |
A Parallelizing Compiler Approach Based on | 720 |
Semantic Web Based Knowledge Searching System in Mobile | 741 |
A GeneralPurpose Intelligent RAIDBased Object Storage Device | 747 |
Improvement of Space Utilization in NAND Flash Memory Storages | 766 |
Citi izdevumi - Skatīt visu
Embedded Software and Systems: Second International Conference, ICESS 2005 ... Laurence T. Yang Ierobežota priekšskatīšana - 2005 |
Bieži izmantoti vārdi un frāzes
algorithm allocation analysis application architecture automata bandwidth Berlin Heidelberg 2005 bioinformatics bits block buffer bytecodes bytes channel clusters communication compiler compiler optimizations components Computer constraints context core deadlock defined delay detect dynamic EEPROM efficiency embedded embedded systems energy consumption evaluation execution Figure Floorplan FPGA frequency functional unit handling task hardware High Level Synthesis I-cache ICESS IEEE implementation input instruction IOMem IPv6 Java Card latency layer linear Linux LNCS load locking cache loop memory access method module monitor O.OOOO operation optimization packet paper parameters parity bits performance prefetching prefix probabilistic timed transition Proc processor proposed protocol RBLS real-time systems router routing scheduling scheme sensor networks sensor nodes sequence simulation SVMAS Table techniques throughput transaction variables VLIW wait-for WCET web service wireless Wireless Sensor Networks workloads