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" D. Lee, D. Blaauw, and D. Sylvester, "Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Circuits, Vol. "
Low Power Methodology Manual: For System-on-Chip Design - 293. lappuse
autors: David Flynn, Rob Aitken, Alan Gibbons, Kaijian Shi - 2007 - 300 lapas
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Power Distribution Networks with On-Chip Decoupling Capacitors

Mikhail Popovich, Andrey Mezhiba, Eby G. Friedman - 2007 - 516 lapas
...Journal of Solid-State Circuits, Vol. 40, No. 3, pp. 719-725, March 2005. 353. D. Lee, D. Blaauw, and D. Sylvester, "Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Circuits, Vol. 12, No. 2, pp. 155-166, February...
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