Low Power Methodology Manual: For System-on-Chip DesignSpringer Science & Business Media, 2007. gada 31. jūl. - 300 lappuses Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach. Richard Goering, Software Editor, EE Times Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion. Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs. Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc. Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management. Nick Salter, Head of Chip Integration, CSR plc. |
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1.5. rezultāts no 62.
... Performance Analysis................... 145 Silicon-Measured ULTRA926 DVFS Energy Savings Analysis.. 147 10.2 Voltage Scaling A worked Example for TSMC 65nm........................... 150 Voltage/Frequency Range Exploration ...
... a significant effect on how chips are designed. The power density of the highest performance chips has grown to the point where it is no longer possible to increase clock speed as technology shrinks. As a CHAPTER 1 Introduction 1.1 ...
... performance. This book describes a number of the techniques designers can use to reduce the power consumption of complex SoC designs. Our approach is practical, rather than theoretical. We draw heavily upon the experience we have gained ...
... performance and features and grow these businesses. Until recently, power has been a second order concern in chip design, following first order issues such as cost, area, and timing. Today, for most SoC designs, the power budget is one ...
... performance, we can provide a high supply voltage and correspondingly high clock frequency. For tasks that require lower performance, we can provide a lower voltage and slower clock. This approach is known as voltage scaling. Another ...
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1 | |
13 | |
20 | |
CHAPTER 4 Power Gating Overview | 33 |
CHAPTER 5 Designing Power Gating | 41 |
CHAPTER 6 Architectural Issues for Power Gating | 74 |
CHAPTER 7 A Power Gating Example | 85 |
CHAPTER 8 IP Design for Low Power | 101 |
CHAPTER 10 Examples of Voltage and Frequency Scaling Design | 139 |
CHAPTER 11 Implementing Multi Voltage Power Gated Designs | 155 |
CHAPTER 12 Physical Libraries | 187 |
CHAPTER 13 Retention Register Design | 208 |
CHAPTER 14 Design of the Power Switching Network | 225 |
APPENDIX B UPF Command Syntax | 267 |
Index | 297 |
CHAPTER 9 Frequency and Voltage Scaling Design | 120 |
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