Low Power Methodology Manual: For System-on-Chip DesignSpringer Science & Business Media, 2007. gada 31. jūl. - 300 lappuses “Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach.” Richard Goering, Software Editor, EE Times “Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion.” Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies “The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs.” Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc. “Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management.” Nick Salter, Head of Chip Integration, CSR plc. |
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1.–5. rezultāts no 55.
... ........ 243 Buffer Delay Based Main Chain Turn-on Control ...................... 243 Parallel Short Chain Distribution of the Main Sleep Transistor... 243 Power-off Latency Reduction ...................................................
... switching power. Figure 1-2 Dynamic Power The energy per transition is given. Figure 1-1 Power vs. Energy Figure 2-5 Leakage vs. Delay for a 90nm Library. 4 Low Power Methodology Manual Figure 1-1 Power vs. Energy 1.4 Dynamic Power.
... delay. In addition, the flops receiving the clock dissipate some dynamic power even if the input and output remain the same. The most common way to reduce this power is to turn clocks off when they are not required. This approach is ...
... delay of the gates in the design. Consider the example in Figure 2-3. Here the cache RAMS are run at the highest voltage because they are on the critical timing path. The CPU is run at a high voltage because its performance determines ...
... delay and leakage for a 90nm process. Figure 2-5 shows some representative curves for leakage vs. delay for a multi-VT library. As explained earlier, sub-threshold leakage depends exponentially on VT. Delay has a much weaker dependence ...
Saturs
1 | |
13 | |
20 | |
CHAPTER 4 Power Gating Overview | 33 |
CHAPTER 5 Designing Power Gating | 41 |
CHAPTER 6 Architectural Issues for Power Gating | 74 |
CHAPTER 7 A Power Gating Example | 85 |
CHAPTER 8 IP Design for Low Power | 101 |
CHAPTER 10 Examples of Voltage and Frequency Scaling Design | 139 |
CHAPTER 11 Implementing Multi Voltage Power Gated Designs | 155 |
CHAPTER 12 Physical Libraries | 187 |
CHAPTER 13 Retention Register Design | 208 |
CHAPTER 14 Design of the Power Switching Network | 225 |
APPENDIX B UPF Command Syntax | 267 |
Index | 297 |
CHAPTER 9 Frequency and Voltage Scaling Design | 120 |
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