Low Power Methodology Manual: For System-on-Chip DesignSpringer Science & Business Media, 2007. gada 31. jūl. - 300 lappuses Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach. Richard Goering, Software Editor, EE Times Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion. Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs. Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc. Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management. Nick Salter, Head of Chip Integration, CSR plc. |
No grāmatas satura
1.5. rezultāts no 60.
... and enabling us to derive the results referenced in the worked examples. Dave Flynn Mike Keating Cambridge, UK Palo Alto, CA CHAPTER 1 Introduction FIGURE 2.0. TABLE 2.0. EXAMPLE 1.0. 1.1 xvi Low Power Methodology Manual.
... CHAPTER 1. Introduction. FIGURE 2.0. TABLE 2.0. EXAMPLE 1.0. 1.1. Overview. The design of complex chips has undergone a series of revolutions during the last twenty years. In the 1980s there was the introduction of language-based design and ...
... chapters. For now, though, we mention three other techniques: VTCMOS Variable Threshold CMOS (VTCMOS) is another very effective way of mitigating standby leakage power. By applying a reverse bias voltage to the substrate, it is possible ...
... make, of course, is what power strategy to pursuewhat techniques to use, when and where and on what section of the chip. This fundamental issue drives the structure of the book. Chapter 1 (this chapter) gives and over view of.
... Chapter 1 (this chapter) gives and over view of the challenges and basic approach to low power design. Chapter 2 discusses clock gating methods, Multi-VT designs, logic-level power reduction techniques, and multi-voltage design ...
Saturs
1 | |
13 | |
20 | |
CHAPTER 4 Power Gating Overview | 33 |
CHAPTER 5 Designing Power Gating | 41 |
CHAPTER 6 Architectural Issues for Power Gating | 74 |
CHAPTER 7 A Power Gating Example | 85 |
CHAPTER 8 IP Design for Low Power | 101 |
CHAPTER 10 Examples of Voltage and Frequency Scaling Design | 139 |
CHAPTER 11 Implementing Multi Voltage Power Gated Designs | 155 |
CHAPTER 12 Physical Libraries | 187 |
CHAPTER 13 Retention Register Design | 208 |
CHAPTER 14 Design of the Power Switching Network | 225 |
APPENDIX B UPF Command Syntax | 267 |
Index | 297 |
CHAPTER 9 Frequency and Voltage Scaling Design | 120 |
Bieži izmantoti vārdi un frāzes
Populāri fragmenti
Atsauces uz šo grāmatu
Digital VLSI Design with Verilog: A Textbook from Silicon Valley Technical ... John Williams Ierobežota priekšskatīšana - 2008 |