Low Power Methodology Manual: For System-on-Chip Design

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Springer Science & Business Media, 2007. gada 31. jūl. - 300 lappuses

“Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach.”

Richard Goering, Software Editor, EE Times

“Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion.”

Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies

“The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs.”

Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc.

“Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management.”

Nick Salter, Head of Chip Integration, CSR plc.

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Atlasītās lappuses

Saturs

CHAPTER 1 Introduction
1
CHAPTER 2 Standard Low Power Methods
13
CHAPTER 3 MultiVoltage Design
20
CHAPTER 4 Power Gating Overview
33
CHAPTER 5 Designing Power Gating
41
CHAPTER 6 Architectural Issues for Power Gating
74
CHAPTER 7 A Power Gating Example
85
CHAPTER 8 IP Design for Low Power
101
CHAPTER 10 Examples of Voltage and Frequency Scaling Design
139
CHAPTER 11 Implementing Multi Voltage Power Gated Designs
155
CHAPTER 12 Physical Libraries
187
CHAPTER 13 Retention Register Design
208
CHAPTER 14 Design of the Power Switching Network
225
APPENDIX B UPF Command Syntax
267
Index
297
Autortiesības

CHAPTER 9 Frequency and Voltage Scaling Design
120

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vi. lappuse - ARM" is used to represent ARM Holdings pic; its operating company ARM Limited; and the regional subsidiaries ARM INC.; ARM KK; ARM Korea Ltd.; ARM Taiwan; ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Belgium NV; AXYS Design Automation Inc.; AXYS GmbH; ARM Embedded Technologies Pvt. Ltd.; and ARM, Inc.
1. lappuse - ... other information valuable to field officers completing the forms. These projects typify rather than describe completely the accomplishments of the Planning and Research Division. As previously indicated departmental acceptance is an index of the worthwhileness of the planning approach. This acceptance has grown to the point where it is no longer possible to perform all the services requested by line units. CONSIDERATIONS It is, therefore, evident that the Planning and Research Division was organized...
293. lappuse - D. Lee, D. Blaauw, and D. Sylvester, "Gate Oxide Leakage Current Analysis and Reduction for VLSI Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Circuits, Vol.
39. lappuse - One of the key challenges in any power gating design is managing the in-rush current when the power is reconnected. This in-rush current must be carefully controlled in order to avoid excessive IR drop in the power network...
39. lappuse - The key advantage of fine grain power gating is that the timing impact of the IR drop across the switch and the behavior of the clamp are easy to characterize as they are contained within the cell.
293. lappuse - K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanism and leakage reduction techniques in deep-submicrometer CMOS circuits", Proc.
vi. lappuse - Inc., or their affiliates be liable for any indirect, special or consequential damages in connection with the information provided herein.

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Par autoru (2007)

ABOUT THE AUTHORS:

Michael Keating is a Synopsys Fellow in the company’s Advanced Technology Group, focusing on IP development methodology, hardware and software design quality and low power design.

David Flynn is an ARM R&D Fellow and has been with the company since 1991, specializing in low power System-on-Chip IP deployment and methodology.

Robert Aitken is an ARM R&D Fellow. His areas of responsibility include memory architecture, design for testability and design for manufacturability.

Alan Gibbons is a Principal Engineer at Synopsys, with a focus on development of advanced methodology and technology for ARM processor-based system design.

Kaijian Shi is a Principal Consultant in the Professional Services Group of Synopsys, specializing in low power design methodology and implementation.

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