Low Power Methodology Manual: For System-on-Chip Design
Springer Science & Business Media, 2007. gada 31. jūl. - 300 lappuses
Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach.
Richard Goering, Software Editor, EE Times
Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion.
Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies
The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs.
Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc.
Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management.
Nick Salter, Head of Chip Integration, CSR plc.
Lietotāju komentāri - Rakstīt atsauksmi
CHAPTER 10 Examples of Voltage and Frequency Scaling Design
CHAPTER 11 Implementing Multi Voltage Power Gated Designs
CHAPTER 12 Physical Libraries
CHAPTER 13 Retention Register Design
CHAPTER 14 Design of the Power Switching Network
APPENDIX B UPF Command Syntax
CHAPTER 9 Frequency and Voltage Scaling Design