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" Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," International Symposium on Low Power Electronics and Design, pp. "
Leakage in Nanometer CMOS Technologies - 42. lappuse
laboja - 2006 - 308 lapas
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Digital Design and Fabrication

Vojin G. Oklobdzija - 2017 - 656 lapas
...technique based on power sensitivity," ACM/IEEE Design Automation Conference, pp. 678-683, June 1998. 13. Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation...considering accurate modeling of transistor stacks," International Symposium on Low Power Electronics and Design, pp. 239-244, 1998. 14. VLSI Microprocessors:...
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The Computer Engineering Handbook

Vojin G. Oklobdzija - 2001 - 1408 lapas
...technique based on power sensitivity," ACM/IEEE Design Automation Conference, pp. 678-683, June 1998. 13. Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation...considering accurate modeling of transistor stacks," International Symposium on Low Power Electronics and Design, pp. 239-244, 1998. 14. VLSI Microprocessors:...
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Multi-Threshold CMOS Digital Circuits: Managing Leakage Power

Mohab Anis, Mohamed Elmasry - 2003 - 216 lapas
...International Conference on Computer Aided Design (1CCAD), pp. 490-496, November 1998. [8] Z. Chen, L. Wei, and K. Roy, "Estimation of Standby Leakage...Considering Accurate Modeling of Transistor Stacks," in Proceedings of the International Symposium on Low-Power Electronics and Design, August 1998, pp....
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Low-Power Electronics Design

Christian Piguet - 2018 - 912 lapas
...IEEE Symp. on VLSI Circuits, 40, June 11-13, 1998. [21] Chen, Z., Wei, L., Johnson, M., and Roy, K., Estimation of standby leakage power in CMOS circuits...considering accurate modeling of transistor stacks, IEEE Int. Conf. on Comput.- Aided Design, Aug. 10-12, 1998. [22] Chen, Z., Wei, L., Keshavarzi, A.,...
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Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits

Manoj Sachdev, José Pineda de Gyvez - 2007 - 328 lapas
...Test Conference 1987, Washington, DC, USA, 1-3 Sept. 1987, pp.3 1-42. 6. Z. Chen, L. Wei, M. Johnson, K. Roy, "Estimation of Standby Leakage Power in CMOS...Considering Accurate Modeling of Transistor Stacks." 7. R. Dekker, F. Beenker, and L. Thijssen, "Fault modeling and Test Algorithm Development for Static...
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Integrated Circuit and System Design. Power and Timing Modeling ...

Nadine Azemard - 2007 - 583 lapas
...Digital Circuit. IEEE J. Solid-State Circuits 31 (May 1996) 5. Cheng, Z., Johnson, M., Wei, L., Roy, K.: Estimation of Standby Leakage Power in CMOS Circuits...Considering Accurate Modeling of Transistor Stacks. In: Proc. Int. Symposium Low Power Electronics and Design, August 1998, pp. 239-244 (1998) 6. Roy,...
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