editions:ISBN0123704901 - Google grāmatas

Z. Ma, P. Moon, P. Nguyen, L. Rumaner, R. Schweinfurth, S. Sivakumar, M. Stettler, S. Thompson, B. Tufts, J. Xu, S. Yang, and M. Bohr, "A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers ofCu interconnects

Leakage in Nanometer CMOS Technologies - 42. lappuse
laboja - 2006 - 308 lapas
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Rapid Thermal and Other Short-time Processing Technologies II: Proceedings ...

Dim-Lee Kwong, Electrochemical Society. Electronics Division, Electrochemical Society. High Temperature Materials Divisions - 2001 - 458 lapas

...groups in Logic Technology Development organization for their support. REFERENCES 1- S. Tyagi et al., "A 130 nm Generation Logic Technology Featuring 70...Vt Transistors and 6 layers of Cu Interconnects", IEDM 2000. 2- T. Ghani et al., "l00nm Gate Length High Performance/Low Power CMOS Transistor structure",...

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Handbook of Semiconductor Manufacturing Technology

Yoshio Nishi, Robert Doering - 2017 - 1720 lapas

...563-6. 17. Tyagi, S., M. Alavi, R. Bigwood, T. Bramblett, J. Brandenburg, W. Chen, B. Crew, et al. "A 130 nm Generation Logic Technology Featuring 70...Transistors, Dual VT Transistors and. 6 layers of interconnects." Tech. Dig. IEEE Int. Interconnect Tech. Conf. (2000): 567-70. 18. Perera, A., B. Smith,...

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