Leakage in Nanometer CMOS TechnologiesSiva G. Narendra, Anantha P. Chandrakasan Springer Science & Business Media, 2006. gada 10. marts - 308 lappuses Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers. |
No grāmatas satura
1.5. rezultāts no 8.
x. lappuse
These leakage currents at the transistor level translate at the system level in
various ways and therefore impact the overall system in a diverse manner. For
example, transistor leakages manifest differently under normal operation
compared to ...
These leakage currents at the transistor level translate at the system level in
various ways and therefore impact the overall system in a diverse manner. For
example, transistor leakages manifest differently under normal operation
compared to ...
1. lappuse
IMPACT,. AND. SOLUTIONS. 1.1 INTRODUCTION Benefits of CMOS technology
scaling in the nanometer regime comes with ... This increase in transistor
leakages not only impacts the overall power consumption of a CMOS system, but
also ...
IMPACT,. AND. SOLUTIONS. 1.1 INTRODUCTION Benefits of CMOS technology
scaling in the nanometer regime comes with ... This increase in transistor
leakages not only impacts the overall power consumption of a CMOS system, but
also ...
2. lappuse
To deal such diverse range of impacts due to transistor leakages, a variety of
solutions is required at all levels of design. The solutions ... Taxonomy of leakage
sources, its impact, and solutions to reduce the impact. Sources originate at the
...
To deal such diverse range of impacts due to transistor leakages, a variety of
solutions is required at all levels of design. The solutions ... Taxonomy of leakage
sources, its impact, and solutions to reduce the impact. Sources originate at the
...
13. lappuse
1.4 SOLUTIONS The above mentioned leakage sources and their dependencies
on environmental parameters make the impact of the leakage sources at the
circuit and system levels quite intricate and diverse. Therefore, there is no one ...
1.4 SOLUTIONS The above mentioned leakage sources and their dependencies
on environmental parameters make the impact of the leakage sources at the
circuit and system levels quite intricate and diverse. Therefore, there is no one ...
113. lappuse
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Saturs
Chapter 6 | 141 |
Chapter 7 | 163 |
Chapter 8 | 200 |
L | 209 |
Chapter 9 | 211 |
Chapter 10 | 234 |
VVV0xW+2+ 20 1 | 236 |
Periphery | 254 |
Chapter 4 | 77 |
11 | 81 |
Vdd I t I | 96 |
botas bbarabosse cseldk14keyb long sandsly | 102 |
Chapter 5 | 105 |
6 | 108 |
aget | 121 |
Chapter 11 | 257 |
i | 269 |
i | 274 |
Chapter 12 | 281 |
B | 291 |
Figure 129 Carbon nanotube structures | 298 |
Citi izdevumi - Skatīt visu
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Ierobežota priekšskatīšana - 2006 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2005 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
active leakage active mode applied biasing burn-in capacitance channel length circuit blocks clock gating CMOS CMOS circuits critical path defective delay diode drain DRAM Drowsy mode dynamic dynamic voltage scaling Electronics flip-flop FMAx frequency gate leakage gating transistors high Vt high-speed IDDQ IEEE impact implementation increase junction leakage current leakage power leakage reduction logic logic gates Low Power lower microprocessor MOSFET MT cells MTCMOS NMOS NMOS transistors node on-chip operation output oxide thickness performance PMOS power gating transistors power supply power switch processor reduce leakage reverse body bias salicide scheme shown in Figure signal silicon sleep devices sleep transistor Solid-State Circuits SRAM SRAM cell stack effect standby leakage standby mode standby power sub-threshold current substrate supply voltage technique technology scaling temperature threshold voltage tunneling VLSI voltage scaling
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Atsauces uz šo grāmatu
Low Power Methodology Manual: For System-on-Chip Design David Flynn,Rob Aitken,Alan Gibbons,Kaijian Shi Ierobežota priekšskatīšana - 2007 |
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |