Leakage in Nanometer CMOS TechnologiesSiva G. Narendra, Anantha P. Chandrakasan Springer Science & Business Media, 2006. gada 10. marts - 308 lappuses Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers. |
No grāmatas satura
1.–5. rezultāts no 68.
vi. lappuse
... Biasing TADAHIRO KURODA AND TAKAYASU SAKURAI 5.1 Introduction 5.2 Reverse Body Bias 5.3 Forward Body Bias 5.4 Future Directions References Process Variation and Adaptive Design SIVA NARENDRA, JAMES TSCHANZ, JAMES KAO, SHEKAR BORKAR ...
... Biasing TADAHIRO KURODA AND TAKAYASU SAKURAI 5.1 Introduction 5.2 Reverse Body Bias 5.3 Forward Body Bias 5.4 Future Directions References Process Variation and Adaptive Design SIVA NARENDRA, JAMES TSCHANZ, JAMES KAO, SHEKAR BORKAR ...
x. lappuse
... biasing, use of multiple performance transistors, leakage reduction in memory, impact of process variation on leakage and design margins, active leakage power reduction techniques, and impact of process variation and leakage on testing ...
... biasing, use of multiple performance transistors, leakage reduction in memory, impact of process variation on leakage and design margins, active leakage power reduction techniques, and impact of process variation and leakage on testing ...
2. lappuse
... biasing, use of multiple performance transistors, leakage reduction in memory, active leakage power reduction techniques, and transistor design choices will explained in detailed in dedicated chapters. Since leakage depends ...
... biasing, use of multiple performance transistors, leakage reduction in memory, active leakage power reduction techniques, and transistor design choices will explained in detailed in dedicated chapters. Since leakage depends ...
10. lappuse
... biased junctions that have heavy dopings on both side results in direct tunneling across these junctions. Furthermore with reducing volume of the transistors the metal silicide being used for source, gate, and drain terminals increase ...
... biased junctions that have heavy dopings on both side results in direct tunneling across these junctions. Furthermore with reducing volume of the transistors the metal silicide being used for source, gate, and drain terminals increase ...
13. lappuse
... biasing technique that allows electrical modulation of transistor threshold voltage is explained and its usage for power reduction is presented. Chapter 6 covers various adaptive design techniques to minimize impact of parameter ...
... biasing technique that allows electrical modulation of transistor threshold voltage is explained and its usage for power reduction is presented. Chapter 6 covers various adaptive design techniques to minimize impact of parameter ...
Saturs
Chapter 6 | 141 |
Chapter 7 | 163 |
Chapter 8 | 200 |
L | 209 |
Chapter 9 | 211 |
Chapter 10 | 234 |
VVV0xW+2+ 20 1 | 236 |
Periphery | 254 |
Chapter 4 | 77 |
11 | 81 |
Vdd I t I | 96 |
botas bbarabosse cseldk14keyb long sandsly | 102 |
Chapter 5 | 105 |
6 | 108 |
aget | 121 |
Chapter 11 | 257 |
i | 269 |
i | 274 |
Chapter 12 | 281 |
B | 291 |
Figure 129 Carbon nanotube structures | 298 |
Citi izdevumi - Skatīt visu
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Ierobežota priekšskatīšana - 2006 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2005 |
Leakage in Nanometer CMOS Technologies Siva G. Narendra,Anantha P. Chandrakasan Priekšskatījums nav pieejams - 2010 |
Bieži izmantoti vārdi un frāzes
achieved active mode adaptive additional allows applied approach becomes biasing block body bias capacitance cause cell channel length Chapter charge chip circuit clock CMOS compared critical defective delay depends described devices drain drive dynamic effect energy example Figure frequency higher IDDQ IEEE impact implementation improve increase input junction larger leakage current leakage power leakage reduction limit logic lower measured microprocessor minimize MOSFET MTCMOS needed NMOS node noise operation output oxide parameter path penalty performance PMOS power gating power supply power switch presented reduce leakage reduced savings scaling scheme selected shown in Figure shows signal sleep transistor smaller solution speed SRAM stack standby mode sub-threshold leakage substrate supply voltage techniques temperature threshold voltage tunneling turned variation virtual width
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Atsauces uz šo grāmatu
Low Power Methodology Manual: For System-on-Chip Design David Flynn,Rob Aitken,Alan Gibbons,Kaijian Shi Ierobežota priekšskatīšana - 2007 |
Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication Hubert Kaeslin Ierobežota priekšskatīšana - 2008 |