Leakage in Nanometer CMOS Technologies

Pirmais vāks
Siva G. Narendra, Anantha P. Chandrakasan
Springer Science & Business Media, 2006. gada 10. marts - 308 lappuses
Scaling transistors into the nanometer regime has resulted in a dramatic increase in MOS leakage (i.e., off-state) current. Threshold voltages of transistors have scaled to maintain performance at reduced power supply voltages. Leakage current has become a major portion of the total power consumption, and in many scaled technologies leakage contributes 30-50% of the overall power consumption under nominal operating conditions. Leakage is important in a variety of different contexts. For example, in desktop applications, active leakage power (i.e., leakage power when the processor is computing) is becoming significant compared to switching power. In battery operated systems, standby leakage (i.e., leakage when the processor clock is turned off) dominates as energy is drawn over long idle periods. Increased transistor leakages not only impact the overall power consumed by a CMOS system, but also reduce the margins available for design due to the strong relationship between process variation and leakage power. It is essential for circuit and system designers to understand the components of leakage, sensitivity of leakage to different design parameters, and leakage mitigation techniques in nanometer technologies. This book provides an in-depth treatment of these issues for researchers and product designers.

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Atlasītās lappuses

Saturs

Chapter 2
21
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25
Chapter 3
40
EQUIVALENT CIRCUITSN
44
f
50
Figure 36 MTCMOS flipflop using parallel high Vt structures
57
Ni N2
61
Figure 39 Leakage feedback MTCMOS flip flop static
62
Chapter 6
141
Chapter 7
163
Chapter 8
200
L
209
Chapter 9
211
Chapter 10
234
VVV0xW+2+ 20 1
236
Periphery
254

Chapter 4
77
11
81
Vdd I t I
96
botas bbarabosse cseldk14keyb long sandsly
102
Chapter 5
105
6
108
aget
121
Chapter 11
257
i
269
i
274
Chapter 12
281
B
291
Figure 129 Carbon nanotube structures
298
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