Software and Compilers for Embedded Systems: 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings

Pirmais vāks
Springer Science & Business Media, 2003. gada 16. sept. - 402 lappuses
This volume contains the proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2003, held in Vienna, Austria, September 24–26, 2003. Initially, the workshop was referred to as the International Workshop on Code Generation for Embedded Systems. The ?rst workshop took place in 1994 in Schloss Dagstuhl, Germany. From its beg- nings, the intention of the organizers was to create an atmosphere in which the researcherscould participateactively in dynamic discussionsand pro?t from the assembly of international experts in the ?eld. It was at the fourth workshop, in St. Goar, Germany, in 1999, that the spectrum of topics of interest for the workshop was extended, and not only code generation, but also software and compilers for embedded systems, were considered. The change in ?elds of interest led to a change of name, and this is when the present name was used for the ?rst time. Since then, SCOPES has been held again in St. Goar, Germany, in 2001; Berlin, Germany, in 2002; and this year, 2003, in Vienna, Austria. In response to the call for papers, 43 very strong papers from all over the world were submitted. The program committee selected 26 papers for pres- tation at SCOPES 2003. All submitted papers were reviewed by at least three experts in order to ensure the quality of the work presented at the workshop.

No grāmatas satura

Lietotāju komentāri - Rakstīt atsauksmi

Ierastajās vietās neesam atraduši nevienu atsauksmi.

Atlasītās lappuses

Saturs

The Transmeta Crusoe
1
Limited Address Range Architecture for Reducing Code Size in Embedded Processors
2
Predicated Instructions for Code Compaction
17
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation
33
Code Instruction Selection Based on SSAGraphs
49
A Code Selection Method for SIMD Processors with PACK Instructions
66
Reconstructing Control Flow from Predicated Assembly Code
81
Control Flow Analysis for Recursion Removal
101
Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor
226
Retargetable GraphColoring Register Allocation for Irregular Architectures
240
FineGrain Register Allocation Based on a Global Spill Costs Analysis
255
Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment
270
Improving Offset Assignment through Simultaneous Variable Coalescing
285
Transformation of Metainformation by Abstract Cointerpretation
298
Performance Analysis for Identification of SubTaskLevel Parallelism in Java
313
Towards Superinstructions for Java Interpreters
329

An UnfoldingBased Loop Optimization Technique
117
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer
133
Case Studies on Automatic Extraction of TargetSpecific Architectural Parameters in Complex Code Generation
151
Extraction of Efficient Instruction Schedulers from CycleTrue Processor Models
167
A Framework for the Design and Validation of Efficient FailSafe FaultTolerant Programs
182
A Case Study on a ComponentBased System and Its Configuration
198
Composable Code Generation for ModelBased Development
211
Partitioning for DSP Software Synthesis
344
Efficient Variable Allocation to Dual Memory Banks of DSPs
359
Cache Behavior Modeling of Codes with DataDependent Conditionals
373
A Fast Instruction Cache Optimizer
388
Author Index
403
Autortiesības

Citi izdevumi - Skatīt visu

Bieži izmantoti vārdi un frāzes

Bibliogrāfiskā informācija