Advanced Computer Architecture and Parallel ProcessingJohn Wiley & Sons, 2005. gada 8. apr. - 288 lappuses Computer architecture deals with the physical configuration, logical structure, formats, protocols, and operational sequences for processing data, controlling the configuration, and controlling the operations over a computer. It also encompasses word lengths, instruction codes, and the interrelationships among the main parts of a computer or group of computers. This two-volume set offers a comprehensive coverage of the field of computer organization and architecture. |
No grāmatas satura
1.–5. rezultāts no 29.
6. lappuse
... memory. Thus, the front end can issue special commands that cause parts of the memory to be operated on ... modules communicate with each other via the interconnection network. Two processors can transfer data between each other via ...
... memory. Thus, the front end can issue special commands that cause parts of the memory to be operated on ... modules communicate with each other via the interconnection network. Two processors can transfer data between each other via ...
8. lappuse
... memory) typically combines the local memory and processor at each node of the interconnection network. There is no global memory, so it is necessary to move data from one local memory to another by means of message passing. This is ...
... memory) typically combines the local memory and processor at each node of the interconnection network. There is no global memory, so it is necessary to move data from one local memory to another by means of message passing. This is ...
9. lappuse
... memory is physically distributed; for example, the hardware architecture follows the message passing school of ... module that can be accessed from two processors. Requests arrive at the memory module through its two ports. An ...
... memory is physically distributed; for example, the hardware architecture follows the message passing school of ... module that can be accessed from two processors. Requests arrive at the memory module through its two ports. An ...
10. lappuse
... memory location directly using its real address. However, the access time to modules depends on the distance to the processor. This results in a nonuniform memory access time. A number of architectures are used to interconnect ...
... memory location directly using its real address. However, the access time to modules depends on the distance to the processor. This results in a nonuniform memory access time. A number of architectures are used to interconnect ...
12. lappuse
... memory and message passing systems. Shared memory systems can be designed using bus-based or switch-based INs. The ... modules. A crossbar switch, which will be discussed further in Chapter 2, can be visualized as a mesh of wires with ...
... memory and message passing systems. Shared memory systems can be designed using bus-based or switch-based INs. The ... modules. A crossbar switch, which will be discussed further in Chapter 2, can be visualized as a mesh of wires with ...
Saturs
1 | |
19 | |
3 Performance Analysis of Multiprocessor Architecture | 51 |
4 Shared Memory Architecture | 77 |
5 Message Passing Architecture | 103 |
6 Abstract Models | 127 |
7 Network Computing | 157 |
8 Parallel Programming in the Parallel Virtual Machine | 181 |
9 Message Passing Interface MPI | 205 |
10 Scheduling and Task Allocation | 235 |
Index | 267 |
Citi izdevumi - Skatīt visu
Advanced Computer Architecture and Parallel Processing Hesham El-Rewini,Mostafa Abd-El-Barr Priekšskatījums nav pieejams - 2005 |
Advanced Computer Architecture and Parallel Processing Hesham El-Rewini,Mostafa Abd-El-Barr Priekšskatījums nav pieejams - 2005 |
Bieži izmantoti vārdi un frāzes
application array assigned bandwidth benchmark binary block broadcast cache coherence called cessors Chapter client Clos network cluster communication delay complexity Computer Architecture connected copy cost crossbar crossbar switch destination distributed dynamic El-Rewini elements Ethernet example execution Gantt chart given global memory grid heuristics hypercube identifier input instance number integer interconnection networks interface interval order k-ary n-cube latency log2 memory modules mesh Message Passing Interface message passing systems MIMD multiple bus multiprocessor multiprocessor system Myrinet n-cube node nonblocking NP-complete number of nodes number of processors operation optimal output packet parallel algorithm Parallel Computing Parallel Processing parallel system parameters path performance PRAM protocol Q reads Q updates Q’s Cache Read-Miss receive buffer request scalability send buffer server shared memory system shown in Figure SIMD spawned speedup factor switch synchronous TABLE task allocation task graph topology workers wormhole routing
Populāri fragmenti
244. lappuse - Scheduling the augmented task graph without considering communication is equivalent to scheduling the original task graph with communication. Algorithm 4 produces an optimal schedule when the task graph is an in-forest. It can be used in the out-forest case with simple modification. We provide the following definitions. 1 Node depth The depth of a node is defined as the length of the longest path from any node with depth zero to that node. A node with no predecessors has a depth of zero. In other...
177. lappuse - CM-5 was provided by the National Center for Supercomputing Applications at the University of Illinois at Urbana-Champaign.
4. lappuse - Cyber-205, made by Control Data Corporation. These computers are capable of performing hundreds of millions of floating-point operations per second. Pipelined vector processors are surveyed in Chapter 11. Processor Arrays A processor array is a set of identical synchronized processing elements capable of simultaneously performing the same operation on different data. Processor arrays are a second way to implement vector computers. To elaborate on the difference between a pipelined vector processor...
253. lappuse - Clusters are not tasks, since tasks that belong to a cluster are permitted to communicate with the tasks of other clusters immediately after the completion of their execution. Clustering heuristics are nonbacktracking heuristics...
264. lappuse - Scheduling Parallel Program Tasks onto Arbitrary Target Machines", Journal of Parallel and Distributed Computing, vol. 9 (1990), pp.
14. lappuse - A network that can handle all possible connections without blocking is called a nonblocking network.
67. lappuse - Corporation (SPEC) was formed to "establish, maintain and endorse a standardized set of relevant benchmarks that can be applied to the newest generation of high-performance computers
74. lappuse - Analyzing Scalability of Parallel Algorithms and Architectures." Journal of Parallel and Distributed Computing, Special Issue on Scalability. Vol. 22. No. 3, September 1994, Pages 379-392.
47. lappuse - Performance analysis of multiple bus interconnection networks with hierarchical requesting model", IEEE Trans.