Advanced Computer Architecture and Parallel Processing

Pirmais vāks
John Wiley & Sons, 2005. gada 8. apr. - 288 lappuses
Computer architecture deals with the physical configuration, logical structure, formats, protocols, and operational sequences for processing data, controlling the configuration, and controlling the operations over a computer. It also encompasses word lengths, instruction codes, and the interrelationships among the main parts of a computer or group of computers. This two-volume set offers a comprehensive coverage of the field of computer organization and architecture.

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Atlasītās lappuses


1 Introduction to Advanced Computer Architecture and Parallel Processing
2 Multiprocessors Interconnection Networks
3 Performance Analysis of Multiprocessor Architecture
4 Shared Memory Architecture
5 Message Passing Architecture
6 Abstract Models
7 Network Computing
8 Parallel Programming in the Parallel Virtual Machine
9 Message Passing Interface MPI
10 Scheduling and Task Allocation

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244. lappuse - Scheduling the augmented task graph without considering communication is equivalent to scheduling the original task graph with communication. Algorithm 4 produces an optimal schedule when the task graph is an in-forest. It can be used in the out-forest case with simple modification. We provide the following definitions. 1 Node depth The depth of a node is defined as the length of the longest path from any node with depth zero to that node. A node with no predecessors has a depth of zero. In other...
177. lappuse - CM-5 was provided by the National Center for Supercomputing Applications at the University of Illinois at Urbana-Champaign.
4. lappuse - Cyber-205, made by Control Data Corporation. These computers are capable of performing hundreds of millions of floating-point operations per second. Pipelined vector processors are surveyed in Chapter 11. Processor Arrays A processor array is a set of identical synchronized processing elements capable of simultaneously performing the same operation on different data. Processor arrays are a second way to implement vector computers. To elaborate on the difference between a pipelined vector processor...
253. lappuse - Clusters are not tasks, since tasks that belong to a cluster are permitted to communicate with the tasks of other clusters immediately after the completion of their execution. Clustering heuristics are nonbacktracking heuristics...
264. lappuse - Scheduling Parallel Program Tasks onto Arbitrary Target Machines", Journal of Parallel and Distributed Computing, vol. 9 (1990), pp.
14. lappuse - A network that can handle all possible connections without blocking is called a nonblocking network.
67. lappuse - Corporation (SPEC) was formed to "establish, maintain and endorse a standardized set of relevant benchmarks that can be applied to the newest generation of high-performance computers
74. lappuse - Analyzing Scalability of Parallel Algorithms and Architectures." Journal of Parallel and Distributed Computing, Special Issue on Scalability. Vol. 22. No. 3, September 1994, Pages 379-392.
47. lappuse - Performance analysis of multiple bus interconnection networks with hierarchical requesting model", IEEE Trans.

Atsauces uz šo grāmatu

Task Scheduling for Parallel Systems
Oliver Sinnen
Ierobežota priekšskatīšana - 2007

Par autoru (2005)

HESHAM EL-REWINI, PHD, PE, is a full professor and chairman of the Department of Computer Sciences and Engineering at Southern Methodist University (SMU). He has co-authored several books, published numerous research papers in journals and conference proceedings, and chaired many international conferences.

MOSTAFA ABD-EL-BARR/strong, PHD, PEnG, is a professor and chairman of the Department of Information Science at Kuwait University. He has co-authored two other books, published more than 120 research papers in journals and conference proceedings, and served as chair for a number of international conferences and symposia.

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