The Designer's Guide to VHDLElsevier, 2001. gada 5. jūn. - 759 lappuses Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals. |
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... the component instance. The architecture body may also contain processes that test that the component instance produces the expected values on its output signals. Alternatively, we may use the 1.4 VHDL Modeling Concepts 13.
... produce may in some cases appear cryptic if we are unaware of the syntax rules. The idea behind EBNF is to divide the language into syntactic categories. For each syntactic category we write a rule that describes how to build a VHDL ...
... produces different values on two successive evaluations. The only time this may occur is if the initialization expression contains a call to a function with side effects (see Chapter 7). Constant and variable declarations can appear in ...
... produce the new value. The type of this value must match the type of the variable. The full details of how an expression is formed are covered in the rest of this chapter. For now, just think of expressions as the usual combinations of ...
... produces zero minus the operand. So, for example, the following all produce the same result: A + ( B), A (+B), A B The division operator produces an integer that is the result of dividing, with any fractional part truncated toward zero ...
Saturs
1 | |
29 | |
57 | |
85 | |
Chapter 5 Basic Modeling Constructs | 107 |
A Pipelined Multiplier Accumulator | 167 |
Chapter 7 Subprograms | 195 |
Chapter 8 Packages and Use Clauses | 231 |
Chapter 17 Access Types and Abstract Data Types | 487 |
Chapter 18 Files and InputOutput | 515 |
Queuing Networks | 549 |
Chapter 20 Attributes and Groups | 585 |
Chapter 21 Miscellaneous Topics | 615 |
Chapter A Synthesis | 639 |
Chapter B The Predefined Package Standard | 655 |
Chapter C IEEE Standard Packages | 659 |
Chapter 9 Aliases | 257 |
A BitVector Arithmetic Package | 267 |
Chapter 11 Resolved Signals | 285 |
Chapter 12 Generic Constants | 309 |
Chapter 13 Generic Constants Components and Configurations | 317 |
Chapter 14 Generate Statements | 349 |
The DLX Computer System | 373 |
Chapter 16 Guards and Blocks | 459 |
Chapter D Related Standards | 671 |
Chapter E VHDL Syntax | 683 |
Chapter F Differences among VHDL87 VHDL93 and VHDL2001 | 697 |
Chapter G Answers to Exercises | 703 |
Chapter H Software Guide | 723 |
References | 743 |
Index | 745 |
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