The Designer's Guide to VHDL

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Elsevier, 2001. gada 5. jūn. - 759 lappuses
3 Atsauksmes


Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.


VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.


This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.

* Details how the new standard allows for increased portability across tools.
* Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.
* Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.
* Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.

No grāmatas satura

 

1.–5. rezultāts no 7.

ix. lappuse
New tools leveraging on VHDL's precise definition continue to be introduced and
offer increased simulation performance, increased synthesis capabilities, and
entirely new capabiliites, such as the formal verification of the functional ...
15. lappuse
A model must be reducible to a collection of signals and processes in order to
simulate it. We can see how ... At some simulation time, a process may be
stimulated by changing the value on a signal to which it is sensitive. The process
is ...
122. lappuse
Thus the process does not see the effect of the assignment until the next time it
resumes, even if this is at the same simulation time. For this reason, a delay of 0
fs in a signal assignment is called a delta delay. To understand why delta delays
 ...
156. lappuse
FIGURE 5-33 A register within the counter structure elaborated down to
architectures that consist only of processes and signals. bit0 bit1 bit2 bit3
Execution Now that we have an elaborated design hierarchy, we can execute it to
simulate ...
623. lappuse
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Atlasītās lappuses

Saturs

Chapter 2 Scalar Data Types and Operations
29
Chapter 3 Sequential Statements
57
Chapter 4 Composite Data Types and Operations
85
Chapter 5 Basic Modeling Constructs
107
A Pipelined Multiplier Accumulator
167
Chapter 7 Subprograms
195
Chapter 8 Packages and Use Clauses
231
Chapter 9 Aliases
257
Chapter 18 Files and InputOutput
515
Queuing Networks
549
Chapter 20 Attributes and Groups
585
Chapter 21 Miscellaneous Topics
615
Chapter A Synthesis
639
Chapter B The Predefined Package Standard
655
Chapter C IEEE Standard Packages
659
Chapter D Related Standards
671

A BitVector Arithmetic Package
267
Chapter 11 Resolved Signals
285
Chapter 12 Generic Constants
309
Chapter 13 Generic Constants Components and Configurations
317
Chapter 14 Generate Statements
349
The DLX Computer System
373
Chapter 16 Guards and Blocks
459
Chapter 17 Access Types and Abstract Data Types
487
Chapter E VHDL Syntax
683
Chapter F Differences among VHDL87 VHDL93 and VHDL2001
697
Chapter G Answers to Exercises
703
Chapter H Software Guide
723
References
743
Index
745
Autortiesības

Citi izdevumi - Skatīt visu

The Designer's Guide to VHDL
Peter J. Ashenden
Ierobežota priekšskatīšana - 2002
The Designer's Guide to VHDL
Peter J. Ashenden
Fragmentu skats - 1996

Bieži izmantoti vārdi un frāzes

actual allow architecture body array association attribute begin behavioral bit_vector block boolean called cell changes Chapter character clock complex component condition configuration constant contains convert counter defined delay described determine Develop downto driver element enable entity entity declaration example executed expression false function identifier IEEE implementation indication initial input instance instantiation instruction integer interface label logic loop memory module natural Note object operand operations output package parameter perform port map position procedure produce provides range record refer represent reset resolved result shown in Figure shows signal signal assignment signed simulation specify standard statement stored string structure subtype syntax rule tion token transaction unit unsigned variable vector VHDL wait write

Populāri fragmenti

43. lappuse - X' all result in false. The logical operators and, or, nand, nor, xor, xnor and not take operands that must be Boolean values, and they produce Boolean results. Figure 2-3 shows the results produced by the binary logical operators. The result of the not operator is true if the operand is false, and false if the operand is true. The operators and, or, nand and nor are called "short-circuit" operators, as they only evaluate the right operand if the left operand does not determine the result.
Iekļauts 11 grāmatās, sākot no 1996. līdz 2008.
660. lappuse - OF std_ulogic; -- resolution function FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; — *** industry standard logic type *** SUBTYPE std_logic IS resolved std_ulogic; -- unconstrained array of std_logic for use in declaring -- signal arrays TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; -- common subtypes SUBTYPE X01 IS resolved std_ulogic RANGE 'X...
Iekļauts 7 grāmatās, sākot no 1993. līdz 2007.
20. lappuse - Other special symbols consist of pairs of characters. The two characters must be typed next to each other, with no intervening space. These symbols are => ** := /= >= <= <> Numbers There are two forms of numbers that can be written in VHDL code: integer literals and real literals. An integer literal simply represents a whole number and consists of digits without a decimal point. Real literals, on the other hand, can represent fractional numbers. They always include a decimal point, which is preceded...
Iekļauts 6 grāmatās, sākot no 1982. līdz 2002.
656. lappuse - TIME; -- predefined numeric subtypes: subtype NATURAL is INTEGER range 0 to INTEGER'HIGH; subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH...
Iekļauts 15 grāmatās, sākot no 1989. līdz 2006.
660. lappuse - All rights reserved 789 — resolution function function resolved ( s : std_ulogic_vector ) return std_ulogic; — *** industry standard logic type *** subtype stdjogic is resolved std_ulogic; — unconstrained array of stdjogic for use in declaring signal arrays type stdjogic_vector is array ( natural range <>) of stdjogic; — common subtypes subtype X01 is resolved std_ulogic range 'X1 to '1 '; — ('X', '0', '1 ') subtype X01Z is resolved std_ulogic range 'X...
Iekļauts 6 grāmatās, sākot no 1992. līdz 2002.
83. lappuse - T if an integer n is odd, or to '0' if it is even. 2. [O 3.1] Write an if statement that, given the year of today's date in the variable year, sets the variable days_in_February to the number of days in February. A year is a leap year if it is divisible by four, except for years that are divisible by 100. 3. [O 3.2] Write a case statement that strips the strength information from a standardlogic variable x. If x is '0
Iekļauts 12 grāmatās, sākot no 1983. līdz 2004.

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Par autoru (2001)

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

Bibliogrāfiskā informācija

QR code for The Designer's Guide to VHDL
NosaukumsThe Designer's Guide to VHDL
AutorsPeter J. Ashenden
Izdevums:2
IzdevējsElsevier, 2001
ISBN0080477151, 9780080477152
Apjoms759 lappuses
  
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