The Designer's Guide to VHDLElsevier, 2001. gada 5. jūn. - 759 lappuses Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals. |
No grāmatas satura
1.5. rezultāts no 81.
... shown in Figure 1-2. This model describes how the controller repeatedly scans each data input and writes a scaled display of the input value. At this top level of abstraction, the structure of a system may be described as an ...
... shown in Figure 1-5. In the functional domain, a register-transfer language (RTL) is often used to specify the operation of a system at this level. Storage of data is represented using register variables, and transformations are represented ...
... Figure 1-9 shows how the reg4 entity might be composed of latches and gates. If we are to describe this in VHDL, we will need entity declarations and architecture bodies for the subsystems, shown in Figure 1-10. Figure 1-11 is a VHDL ...
... diagram is shown in Figure 4-2. The symbol other represents a character other than 'a', 't', 'd', 'h', a digit or cr. An outline of a process that implements the FSM is shown in Figure 4-3. The type declarations for symbol and state ...
Peter J. Ashenden. FIGURE 5-6 EXAMPLE Let us return to the model of a two-input multiplexer shown in Figure 5-4. The process in that model is sensitive to all three input signals. This means that it will resume on changes on either data ...
Saturs
1 | |
29 | |
57 | |
85 | |
107 | |
A Pipelined Multiplier Accumulator | 167 |
Chapter 7 Subprograms | 195 |
Chapter 8 Packages and Use Clauses | 231 |
Chapter 17 Access Types and Abstract Data Types | 487 |
Chapter 18 Files and InputOutput | 515 |
Queuing Networks | 549 |
Chapter 20 Attributes and Groups | 585 |
Chapter 21 Miscellaneous Topics | 615 |
Chapter A Synthesis | 639 |
Chapter B The Predefined Package Standard | 655 |
Chapter C IEEE Standard Packages | 659 |
Chapter 9 Aliases | 257 |
A BitVector Arithmetic Package | 267 |
Chapter 11 Resolved Signals | 285 |
Chapter 12 Generic Constants | 309 |
Chapter 13 Generic Constants Components and Configurations | 317 |
Chapter 14 Generate Statements | 349 |
The DLX Computer System | 373 |
Chapter 16 Guards and Blocks | 459 |
Chapter D Related Standards | 671 |
Chapter E VHDL Syntax | 683 |
Chapter F Differences among VHDL87 VHDL93 and VHDL2001 | 697 |
Chapter G Answers to Exercises | 703 |
Chapter H Software Guide | 723 |
References | 743 |
Index | 745 |
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