The Designer's Guide to VHDLElsevier, 2001. gada 5. jūn. - 759 lappuses Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals. |
No grāmatas satura
1.–5. rezultāts no 90.
... range of systems from the low-level gates that make up the components to the toplevel functional units. If we are to encompass this range of views of digital systems, we must recognize the complexity with which we are dealing. It is not ...
... range 0 to 100; type oranges is range 0 to 100; we may not assign a value of type apples to a variable of type oranges, since they are of different types. An important use of types is to specify the allowed values for ports of an entity ...
... range. We can define a new integer type using a range-constraint type definition. The simplified syntax rule for an integer type definition is integer_type_definition ⇐ range simple_expression (to I downto) simple_expression which ...
... range of the type. For ascending ranges, this will be the least value, and for descending ranges, it will be the greatest value. If we have these declarations: type set_index_range is range 21 downto 11; type mode_pos_range is 2.2 ...
Peter J. Ashenden. type set_index_range is range 21 downto 11; type mode_pos_range is range 5 to 7; variable set_index : set_index_range; variable mode_pos : mode_pos_range; the initial value of set_index is 21, and that of mode_pos is 5 ...
Saturs
1 | |
29 | |
57 | |
85 | |
107 | |
A Pipelined Multiplier Accumulator | 167 |
Chapter 7 Subprograms | 195 |
Chapter 8 Packages and Use Clauses | 231 |
Chapter 17 Access Types and Abstract Data Types | 487 |
Chapter 18 Files and InputOutput | 515 |
Queuing Networks | 549 |
Chapter 20 Attributes and Groups | 585 |
Chapter 21 Miscellaneous Topics | 615 |
Chapter A Synthesis | 639 |
Chapter B The Predefined Package Standard | 655 |
Chapter C IEEE Standard Packages | 659 |
Chapter 9 Aliases | 257 |
A BitVector Arithmetic Package | 267 |
Chapter 11 Resolved Signals | 285 |
Chapter 12 Generic Constants | 309 |
Chapter 13 Generic Constants Components and Configurations | 317 |
Chapter 14 Generate Statements | 349 |
The DLX Computer System | 373 |
Chapter 16 Guards and Blocks | 459 |
Chapter D Related Standards | 671 |
Chapter E VHDL Syntax | 683 |
Chapter F Differences among VHDL87 VHDL93 and VHDL2001 | 697 |
Chapter G Answers to Exercises | 703 |
Chapter H Software Guide | 723 |
References | 743 |
Index | 745 |
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