The Designer's Guide to VHDL
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No grāmatas satura
1.5. rezultāts no 5.
In many models, the behavior depends on a set of conditions that may or may not
hold true during the course of ... end if; The Boolean expression after the keyword
if is the condition that is used to control whether or not the statement after the ...
operand := address_operand; end if; In this example, the first condition is
evaluated, and if true, the statement after the first then keyword is executed. If the
first condition is false, the second condition is evaluated, and if it evaluates to true
, the ...
While Loops We can augment the basic loop statement introduced previously to
form a while loop, which tests a condition before each iteration. If the condition is
true, iteration proceeds. If it is false, the loop is terminated. The syntax rule for a ...
... condition is true, and the for loop iterates with the loop parameter assuming
successive values from the discrete range. If the condition in a while loop is
initially false, or if the discrete range in a for loop is a null range, then no
iterations occur.
true when the wait statement is executed, the process will still suspend until the
appropriate signals change and cause the condition to be true again. If the wait
statement doesn't include a sensitivity clause, the condition is tested whenever
an ...
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Saturs
29 | |
57 | |
85 | |
107 | |
A Pipelined Multiplier Accumulator | 167 |
Chapter 7 Subprograms | 195 |
Chapter 8 Packages and Use Clauses | 231 |
Chapter 9 Aliases | 257 |
Chapter 18 Files and InputOutput | 515 |
Queuing Networks | 549 |
Chapter 20 Attributes and Groups | 585 |
Chapter 21 Miscellaneous Topics | 615 |
Chapter A Synthesis | 639 |
Chapter B The Predefined Package Standard | 655 |
Chapter C IEEE Standard Packages | 659 |
Chapter D Related Standards | 671 |
A BitVector Arithmetic Package | 267 |
Chapter 11 Resolved Signals | 285 |
Chapter 12 Generic Constants | 309 |
Chapter 13 Generic Constants Components and Configurations | 317 |
Chapter 14 Generate Statements | 349 |
The DLX Computer System | 373 |
Chapter 16 Guards and Blocks | 459 |
Chapter 17 Access Types and Abstract Data Types | 487 |
Chapter E VHDL Syntax | 683 |
Chapter F Differences among VHDL87 VHDL93 and VHDL2001 | 697 |
Chapter G Answers to Exercises | 703 |
Chapter H Software Guide | 723 |
References | 743 |
Index | 745 |
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