The Designer's Guide to VHDL
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No grāmatas satura
1.5. rezultāts no 5.
For example, most clocked devices require that the clock pulse be longer than
some minimum duration. We can use the predefined primary now in an
expression to calculate durations. We return to now in a later chapter. Suffice it to
say that it ...
A discrete event simulator must have a simulation time clock, and when a signal
assignment statement is executed, the delay specified is added to the current
simulation time to determine when the new value is to be applied to the signal.
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Saturs
29 | |
57 | |
85 | |
107 | |
A Pipelined Multiplier Accumulator | 167 |
Chapter 7 Subprograms | 195 |
Chapter 8 Packages and Use Clauses | 231 |
Chapter 9 Aliases | 257 |
Chapter 18 Files and InputOutput | 515 |
Queuing Networks | 549 |
Chapter 20 Attributes and Groups | 585 |
Chapter 21 Miscellaneous Topics | 615 |
Chapter A Synthesis | 639 |
Chapter B The Predefined Package Standard | 655 |
Chapter C IEEE Standard Packages | 659 |
Chapter D Related Standards | 671 |
A BitVector Arithmetic Package | 267 |
Chapter 11 Resolved Signals | 285 |
Chapter 12 Generic Constants | 309 |
Chapter 13 Generic Constants Components and Configurations | 317 |
Chapter 14 Generate Statements | 349 |
The DLX Computer System | 373 |
Chapter 16 Guards and Blocks | 459 |
Chapter 17 Access Types and Abstract Data Types | 487 |
Chapter E VHDL Syntax | 683 |
Chapter F Differences among VHDL87 VHDL93 and VHDL2001 | 697 |
Chapter G Answers to Exercises | 703 |
Chapter H Software Guide | 723 |
References | 743 |
Index | 745 |
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