The Designer's Guide to VHDLElsevier, 2001. gada 5. jūn. - 759 lappuses Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs. VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools. This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on Amazon.com have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals. |
No grāmatas satura
1.–5. rezultāts no 85.
... bit_vector, declared as type bit_vector is array (natural range <>) of bit; This type can be used to represent words of data at the architectural level of modeling. For example, subtypes for representing bytes of data in a little-endian ...
... bit_vector is such a type. However, the standard-logic type std_ulogic_vector is not. We may use string literals for array types such as std_ulogic_vector. Unconstrained Array Ports An important use of an unconstrained array type is to ...
Peter J. Ashenden. 4.3. signal count_value : bit_vector(7 downto 0); signal terminal_count : bit; We instantiate the entity, connecting its input port to the bit-vector signal: tc_gate : entity work.and_multiple(behavioral) port map (i ...
... bit_vector(0 to 15); subtype little_endian_upper_halfword is bit_vector(31 downto 16); variable big : big_endian_upper_halfword; variable little : little_endian_upper_halfword; we could make the following assignments without including ...
... std_ulogic_vector(14 downto 0); data : out std_ulogic_vector(7 downto 0); enable : in std_ulogic); (continued on page 110) (continued from page 109) 5.2 subtype instruction_byte is bit_vector(7 downto 5.1 Entity Declarations 109.
Saturs
1 | |
29 | |
57 | |
85 | |
107 | |
A Pipelined Multiplier Accumulator | 167 |
Chapter 7 Subprograms | 195 |
Chapter 8 Packages and Use Clauses | 231 |
Chapter 17 Access Types and Abstract Data Types | 487 |
Chapter 18 Files and InputOutput | 515 |
Queuing Networks | 549 |
Chapter 20 Attributes and Groups | 585 |
Chapter 21 Miscellaneous Topics | 615 |
Chapter A Synthesis | 639 |
Chapter B The Predefined Package Standard | 655 |
Chapter C IEEE Standard Packages | 659 |
Chapter 9 Aliases | 257 |
A BitVector Arithmetic Package | 267 |
Chapter 11 Resolved Signals | 285 |
Chapter 12 Generic Constants | 309 |
Chapter 13 Generic Constants Components and Configurations | 317 |
Chapter 14 Generate Statements | 349 |
The DLX Computer System | 373 |
Chapter 16 Guards and Blocks | 459 |
Chapter D Related Standards | 671 |
Chapter E VHDL Syntax | 683 |
Chapter F Differences among VHDL87 VHDL93 and VHDL2001 | 697 |
Chapter G Answers to Exercises | 703 |
Chapter H Software Guide | 723 |
References | 743 |
Index | 745 |
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