The Designer's Guide to VHDL

Pirmais vāks
Elsevier, 2001. gada 5. jūn. - 759 lappuses

Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.

VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.

This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.

* Details how the new standard allows for increased portability across tools.
* Covers related standards, including the Numeric Synthesis Package and the Synthesis Operability Package, demonstrating how they can be used for digital systems design.
* Presents four extensive case studies to demonstrate and combine features of the language taught across multiple chapters.
* Requires only a minimal background in programming, making it an excellent tutorial for anyone in computer architecture, digital systems engineering, or CAD.

No grāmatas satura


Chapter 17 Access Types and Abstract Data Types
Chapter 18 Files and InputOutput
Queuing Networks
Chapter 20 Attributes and Groups
Chapter 21 Miscellaneous Topics
Chapter A Synthesis
Chapter B The Predefined Package Standard
Chapter C IEEE Standard Packages

Chapter 9 Aliases
A BitVector Arithmetic Package
Chapter 11 Resolved Signals
Chapter 12 Generic Constants
Chapter 13 Generic Constants Components and Configurations
Chapter 14 Generate Statements
The DLX Computer System
Chapter 16 Guards and Blocks
Chapter D Related Standards
Chapter E VHDL Syntax
Chapter F Differences among VHDL87 VHDL93 and VHDL2001
Chapter G Answers to Exercises
Chapter H Software Guide

Citi izdevumi - Skatīt visu

Bieži izmantoti vārdi un frāzes

Populāri fragmenti

43. lappuse - X' all result in false. The logical operators and, or, nand, nor, xor, xnor and not take operands that must be Boolean values, and they produce Boolean results. Figure 2-3 shows the results produced by the binary logical operators. The result of the not operator is true if the operand is false, and false if the operand is true. The operators and, or, nand and nor are called "short-circuit" operators, as they only evaluate the right operand if the left operand does not determine the result.
660. lappuse - OF std_ulogic; -- resolution function FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; — *** industry standard logic type *** SUBTYPE std_logic IS resolved std_ulogic; -- unconstrained array of std_logic for use in declaring -- signal arrays TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; -- common subtypes SUBTYPE X01 IS resolved std_ulogic RANGE 'X...
20. lappuse - Other special symbols consist of pairs of characters. The two characters must be typed next to each other, with no intervening space. These symbols are => ** := /= >= <= <> Numbers There are two forms of numbers that can be written in VHDL code: integer literals and real literals. An integer literal simply represents a whole number and consists of digits without a decimal point. Real literals, on the other hand, can represent fractional numbers. They always include a decimal point, which is preceded...
656. lappuse - TIME; -- predefined numeric subtypes: subtype NATURAL is INTEGER range 0 to INTEGER'HIGH; subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH...
660. lappuse - All rights reserved 789 — resolution function function resolved ( s : std_ulogic_vector ) return std_ulogic; — *** industry standard logic type *** subtype stdjogic is resolved std_ulogic; — unconstrained array of stdjogic for use in declaring signal arrays type stdjogic_vector is array ( natural range <>) of stdjogic; — common subtypes subtype X01 is resolved std_ulogic range 'X1 to '1 '; — ('X', '0', '1 ') subtype X01Z is resolved std_ulogic range 'X...
83. lappuse - T if an integer n is odd, or to '0' if it is even. 2. [O 3.1] Write an if statement that, given the year of today's date in the variable year, sets the variable days_in_February to the number of days in February. A year is a leap year if it is divisible by four, except for years that are divisible by 100. 3. [O 3.2] Write a case statement that strips the strength information from a standardlogic variable x. If x is '0

Par autoru (2001)

Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.

Bibliogrāfiskā informācija