PARLE '94: Parallel Architectures and Languages Europe : 6th International PARLE Conference, Athens, Greece, July 4-8, 1994 : ProceedingsCostas Halatsis Springer-Verlag, 1994 - 836 lappuses "This volume presents the proceedings of the 5th International Conference Parallel Architectures and Languages Europe (PARLE '94), held in Athens, Greece in July 1994. PARLE is the main Europe-based event on parallel processing. Parallel processing is now well established within the high-performance computing technology and of stategic importance not only to the computer industry, but also for a wide range of applications affecting the whole economy. The 60 full papers and 24 poster presentations accepted for this proceedings were selected from some 200 submissions by the international program committee; they cover the whole field and give a timely state-of-the-art report on research and advanced applications in parallel computing."--PUBLISHER'S WEBSITE. |
No grāmatas satura
1.–3. rezultāts no 85.
580. lappuse
... processor ranges from one to ten . Table 1 clearly shows that processor utilization increases as more loop in- stances are activated . The table shows that when the network latency is 10 cycles , approximately 96 % of the maximum processor ...
... processor ranges from one to ten . Table 1 clearly shows that processor utilization increases as more loop in- stances are activated . The table shows that when the network latency is 10 cycles , approximately 96 % of the maximum processor ...
593. lappuse
... processor as Q , viz . , Z , i.e. , P = Z S3 : else { Identify processor ( s ) with the minimum load ( load = Σ E ) ; S4 : $ 5 : $ 55 } ; Select the processor closest to Z , say Y , from these ; Re - evaluate cost C ( T , Q ) assuming ...
... processor as Q , viz . , Z , i.e. , P = Z S3 : else { Identify processor ( s ) with the minimum load ( load = Σ E ) ; S4 : $ 5 : $ 55 } ; Select the processor closest to Z , say Y , from these ; Re - evaluate cost C ( T , Q ) assuming ...
692. lappuse
... processor i as v and vice - versa . The min - heap property is kept strictly across all the processors ; i.e. , in every processor all items are smaller than those of its children . We call this property the global heap property . Let q ...
... processor i as v and vice - versa . The min - heap property is kept strictly across all the processors ; i.e. , in every processor all items are smaller than those of its children . We call this property the global heap property . Let q ...
Saturs
Improved Probabilistic Routing on Generalized Hypercubes | 1 |
Efficient Communication in the Folded Petersen Interconnection Networks | 25 |
P Lincoln N MartíOliet J Meseguer L Ricciulli | 49 |
Autortiesības | |
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PARLE '94 Parallel Architectures and Languages Europe: 6th International ... Costas Halatsis Ierobežota priekšskatīšana - 1994 |
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Abstract and-goal application architecture array assignment block broadcasting cache cell compiler Computer Science concurrent data tiles defined delay denote dependence Distributed Computing distributed memory distributed shared memory dynamic edge efficient elements evaluation example execution Figure function garbage collector graph rewriting heuristic hypercube hypergrid IEEE implementation interconnection network iterations language latency Lemma load balancing loop machine mapping matrix mesh MIMD/SIMD multiple multiprocessor node number of processors operation optimal output overhead packets parallel algorithms Parallel and Distributed parallel computer parallel program partitioning performance Petersen graph Petri net phase polynomial priority priority queue problem Proc protocol queue reduce reference rewrite rules routing scheduling scheme Section sequence sequential shared memory SIMD simulation single node speedup step strategy structure synchronization task graph technique Theorem threads topology tree updated variables vector vertical virtual channels visualization