PARLE '94: Parallel Architectures and Languages Europe : 6th International PARLE Conference, Athens, Greece, July 4-8, 1994 : ProceedingsCostas Halatsis Springer-Verlag, 1994 - 836 lappuses "This volume presents the proceedings of the 5th International Conference Parallel Architectures and Languages Europe (PARLE '94), held in Athens, Greece in July 1994. PARLE is the main Europe-based event on parallel processing. Parallel processing is now well established within the high-performance computing technology and of stategic importance not only to the computer industry, but also for a wide range of applications affecting the whole economy. The 60 full papers and 24 poster presentations accepted for this proceedings were selected from some 200 submissions by the international program committee; they cover the whole field and give a timely state-of-the-art report on research and advanced applications in parallel computing."--PUBLISHER'S WEBSITE. |
No grāmatas satura
1.–3. rezultāts no 81.
198. lappuse
... Figure 5. The locations of spheres , representing processors , are determined by the percentages of time spent in each of the three states , busy , idle , and overhead . To accomplish these goals , it is necessary to represent both the ...
... Figure 5. The locations of spheres , representing processors , are determined by the percentages of time spent in each of the three states , busy , idle , and overhead . To accomplish these goals , it is necessary to represent both the ...
247. lappuse
... Figure 4. Speedup vs. Number of Processors in the Distributed Shared Memory Mode of Operations ( C = 5 ) Gauss - Jordan 60 50 40 Speedup 30 20 10 4 5 6 Frontier Cholesky Gauss - Jordan Number of Channels Figure 5. Impact of Changing the ...
... Figure 4. Speedup vs. Number of Processors in the Distributed Shared Memory Mode of Operations ( C = 5 ) Gauss - Jordan 60 50 40 Speedup 30 20 10 4 5 6 Frontier Cholesky Gauss - Jordan Number of Channels Figure 5. Impact of Changing the ...
358. lappuse
... Figure 6 : The marionette of data tile 21 , with respect to the given memory assign- ment and the first slot in caches C2 and C4 . Leaves 4 , 6 , and 11 are free , leaf 20 is a fringe leaf , and leaf 8 is blocked . Figure 5 illustrates ...
... Figure 6 : The marionette of data tile 21 , with respect to the given memory assign- ment and the first slot in caches C2 and C4 . Leaves 4 , 6 , and 11 are free , leaf 20 is a fringe leaf , and leaf 8 is blocked . Figure 5 illustrates ...
Saturs
Improved Probabilistic Routing on Generalized Hypercubes | 1 |
Efficient Communication in the Folded Petersen Interconnection Networks | 25 |
P Lincoln N MartíOliet J Meseguer L Ricciulli | 49 |
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PARLE '94 Parallel Architectures and Languages Europe: 6th International ... Costas Halatsis Ierobežota priekšskatīšana - 1994 |
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Abstract and-goal application architecture array assignment block broadcasting cache cell compiler Computer Science concurrent data tiles defined delay denote dependence Distributed Computing distributed memory distributed shared memory dynamic edge efficient elements evaluation example execution Figure function garbage collector graph rewriting heuristic hypercube hypergrid IEEE implementation interconnection network iterations language latency Lemma load balancing loop machine mapping matrix mesh MIMD/SIMD multiple multiprocessor node number of processors operation optimal output overhead packets parallel algorithms Parallel and Distributed parallel computer parallel program partitioning performance Petersen graph Petri net phase polynomial priority priority queue problem Proc protocol queue reduce reference rewrite rules routing scheduling scheme Section sequence sequential shared memory SIMD simulation single node speedup step strategy structure synchronization task graph technique Theorem threads topology tree updated variables vector vertical virtual channels visualization