Compilation Techniques for Reconfigurable Architectures
Springer Science & Business Media, 2011. gada 2. apr. - 223 lappuses
The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures.
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Overview of Reconfigurable Architectures
Compilation and Synthesis Flows
Mapping and Execution Optimizations
Compilers for Reconfigurable Architectures
ACM Press Alamitos algorithm analysis application approach array variables bit-level bit-width bits clock cycles coarse-grained reconfigurable architectures code transformations compilation and synthesis compilation flow compilation techniques Computer Society Press concurrency Conf configuration context Custom Computing Machines data-flow data-path depicted in Fig Design example execution models exploit Field-Programmable Field-Programmable Gate Arrays fine-grained reconfigurable architectures FPGAs FU FU FU function graph hardware compilation hardware implementation hardware resources high-level synthesis IEEE Computer Society IEEE Symp input instructions interconnection Intl iteration latency logic synthesis loop control loop fusion loop pipelining loop tiling loop transformations loop unrolling Los Alamitos memory accesses module multiple operations optimizations parallelism performance pipelined execution placement and routing Proc processor programming languages reconfig reconfigurable architectures reconfigurable computing rely reuse scheduling Software source code spatial partitioning specific speculative execution storage structures synthesis tools Systems target architecture task temporal partitioning tion VHDL VLIW Xilinx Xputer