Compilation Techniques for Reconfigurable ArchitecturesSpringer Science & Business Media, 2011. gada 2. apr. - 223 lappuses The extreme ?exibility of recon?gurable architectures and their performance pot- tial have made them a vehicle of choice in a wide range of computing domains, from rapid circuit prototyping to high-performance computing. The increasing availab- ity of transistors on a die has allowed the emergence of recon?gurable architectures with a large number of computing resources and interconnection topologies. To - ploit the potential of these recon?gurable architectures, programmers are forced to map their applications, typically written in high-level imperative programming l- guages, such as C or MATLAB, to hardware-oriented languages such as VHDL or Verilog. In this process, they must assume the role of hardware designers and software programmers and navigate a maze of program transformations, mapping, and synthesis steps to produce ef?cient recon?gurable computing implementations. The richness and sophistication of any of these application mapping steps make the mapping of computations to these architectures an increasingly daunting process. It is thus widely believed that automatic compilation from high-level programming languages is the key to the success of recon?gurable computing. This book describes a wide range of code transformations and mapping te- niques for programs described in high-level programming languages, most - tably imperative languages, to recon?gurable architectures. |
Saturs
| 1 | |
| 7 | |
Compilation and Synthesis Flows | 33 |
Code Transformations | 66 |
Mapping and Execution Optimizations | 109 |
Compilers for Reconfigurable Architectures | 155 |
Perspectives on Programming ReconfigurableComputing Platforms | 177 |
Final Remarks | 190 |
References | 193 |
List of Acronyms | 213 |
Index | 217 |
Citi izdevumi - Skatīt visu
Compilation Techniques for Reconfigurable Architectures João M.P. Cardoso,Pedro C. Diniz Priekšskatījums nav pieejams - 2010 |
Compilation Techniques for Reconfigurable Architectures João M.P. Cardoso,Pedro C. Diniz Priekšskatījums nav pieejams - 2008 |
Bieži izmantoti vārdi un frāzes
ACM Press Alamitos algorithm analysis application approach array variables bit-level bit-width bits clock cycles coarse-grained reconfigurable architectures compilation and synthesis compilation flow compilation techniques Computer Society Press concurrency Conf configuration context Custom Computing Machines data-path depicted in Fig Design example execution models exploit Field-Programmable Field-Programmable Gate Arrays fine-grained reconfigurable architectures FPGAs FPGAs for Custom FU FU FU function graph hardware implementation hardware resources high-level synthesis IEEE Computer Society IEEE Symp input instructions Integrated interconnection Intl iteration latency logic synthesis loop control loop fusion loop pipelining loop tiling loop transformations loop unrolling Los Alamitos memory accesses module multiple operations optimizations parallelism performance pipelined execution placement and routing Proc processor programming languages reconfig reconfigurable architectures reconfigurable computing rely representation RF RF RF scalar scheduling Software source code spatial partitioning specific speculative execution structures synthesis tools Systems target architecture temporal partitioning tion VHDL VLIW Xilinx Xputer