FPGA Design Automation: A SurveyNow Publishers Inc, 2006 - 140 lappuses FPGA Design Automation: A Survey is an up-to-date comprehensive survey/tutorial of FPGA design automation, with an emphasis on the recent developments within the past 5 to 10 years. The focus is on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. FPGA Design Automation: A Survey can be used as both a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field. |
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1.–5. rezultāts no 27.
7. lappuse
... Design Automation Vol . 1 , No 3 ( November 2006 ) ... gate arrays ( FPGAs ) has played a critical role in the rapid advancement ... architecture - specific optimization , physical synthesis , RT - level and behavior - level synthesis , and power ...
... Design Automation Vol . 1 , No 3 ( November 2006 ) ... gate arrays ( FPGAs ) has played a critical role in the rapid advancement ... architecture - specific optimization , physical synthesis , RT - level and behavior - level synthesis , and power ...
11. lappuse
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Saturs
1. sadaļa | 9 |
2. sadaļa | 11 |
3. sadaļa | 23 |
4. sadaļa | 31 |
5. sadaļa | 45 |
6. sadaļa | 71 |
7. sadaļa | 87 |
8. sadaļa | 99 |
9. sadaļa | 100 |
10. sadaļa | 107 |
11. sadaļa | 131 |
137 | |
Bieži izmantoti vārdi un frāzes
approach area cost Behavior-Level Synthesis behavioral synthesis binding circuit combined components cone connections constraints CPLD critical paths cut selection datapath decomposition detailed routing dynamic power effective area EMBs fanin fanout final mapping solution Floorplanning FPGA architectures FPGA chips FPGA device FPGA routing global and detailed global routing heuristic implementation improve input interconnect delays iteration label layout leakage power logic block logic cells logic synthesis LUTs mapping algorithms module multiplexers netlist nets node NP-hard optimization output p-term performance physical synthesis placement and routing Placement for FPGAs Placement-Driven power consumption power estimation power gating power reduction problem reduce replication retiming rewiring rithm routability router Routing and Placement routing-resource graph RTL synthesis runtime sequential simulated simulated annealing slack SRAM static power Structural Mapping switching activity Synthesis with Higher target technology mapping threshold voltage tion topological order topology tree Verilog VHDL voltage wire segments wirelength Xilinx
Populāri fragmenti
138. lappuse - VPR: A New Packing, Placement and Routing Tool for FPGA Research,
146. lappuse - 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, vol.
149. lappuse - S. Yamashita, H. Sawada, and A. Nagoya. A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications.
138. lappuse - F. Assaderaghi. D. Sinitsky, SA Parke, J. Bokor, PK Ko, and C. Hu, "Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI", IEEE Transactions on Electron Devices.
140. lappuse - Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays" , ACM Trans, on Design Automation of Electronic Systems, Vol.
138. lappuse - V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs.
137. lappuse - Circuits, 25, 1217-1225, 1990. [2] E. Ahmed and J. Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density, Proceedings of the Eighth International Symposium on FPGAs, 2000, pp.
142. lappuse - LA. Entrena and K.-T. Cheng, Combinational and sequential logic optimization by redundancy addition and removal, IEEE Trans.
148. lappuse - A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme,
145. lappuse - A. Marquardt, V. Betz, and J. Rose, Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density, Proceedings of the Seventh International Symposium on FPGAs, 1999, pp.
Atsauces uz šo grāmatu
Compilation Techniques for Reconfigurable Architectures João M.P. Cardoso,Pedro C. Diniz Ierobežota priekšskatīšana - 2011 |
FPGA Architecture: Survey and Challenges Ian Kuon,Russell Tessier,Jonathan Rose Ierobežota priekšskatīšana - 2008 |