FPGA Design Automation: A SurveyFPGA Design Automation: A Survey is an up-to-date comprehensive survey/tutorial of FPGA design automation, with an emphasis on the recent developments within the past 5 to 10 years. The focus is on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. FPGA Design Automation: A Survey can be used as both a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field. |
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Bieži izmantoti vārdi un frāzes
algorithm ASIC behavior synthesis CAPRI channel choice node clock tree COBRA-ABS computer-aided design Config SRAMs connected graph constraints CPLD critical paths datapath decomposition defined delay design specification detailed routing different duplicate dynamic power effective area estimated fanout count example fanin final mapping solution find fixed FloorPlanner FPGA chips FPGA core FPGA global routing FPGA routing architecture function hierarchy high-current path high-level synthesis IMap implementation input iterative label layout Layout-driven logic blocks logic synthesis LUTs macrocell Manhattan distance mapping and clustering mapping graph metric space module instances nect netlist node represents optimization output p-terms partitioning placement Power gating architecture programmable programmable logic device replicate retiming router routing resource graph runtime selected set-covering short-circuit power significant specification languages standard cell designs standby Structural Mapping structural tree switch block switching activity switching power synthesis flow techniques technology mapping tion topologies tree in 83 Verilog VHDL Xilinx
Populāri fragmenti
138. lappuse - VPR: A New Packing, Placement and Routing Tool for FPGA Research,
146. lappuse - 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE Journal of Solid-State Circuits, vol.
149. lappuse - S. Yamashita, H. Sawada, and A. Nagoya. A New Method to Express Functional Permissibilities for LUT based FPGAs and Its Applications.
138. lappuse - F. Assaderaghi. D. Sinitsky, SA Parke, J. Bokor, PK Ko, and C. Hu, "Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI", IEEE Transactions on Electron Devices.
140. lappuse - Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays" , ACM Trans, on Design Automation of Electronic Systems, Vol.
138. lappuse - V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs.
137. lappuse - Circuits, 25, 1217-1225, 1990. [2] E. Ahmed and J. Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density, Proceedings of the Eighth International Symposium on FPGAs, 2000, pp.
142. lappuse - LA. Entrena and K.-T. Cheng, Combinational and sequential logic optimization by redundancy addition and removal, IEEE Trans.
148. lappuse - A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme,
145. lappuse - A. Marquardt, V. Betz, and J. Rose, Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density, Proceedings of the Seventh International Symposium on FPGAs, 1999, pp.
Atsauces uz šo grāmatu
Compilation Techniques for Reconfigurable Architectures João M.P. Cardoso,Pedro C. Diniz Ierobežota priekšskatīšana - 2011 |
FPGA Architecture: Survey and Challenges Ian Kuon,Russell Tessier,Jonathan Rose Ierobežota priekšskatīšana - 2008 |
Bibliogrāfiskā informācija
| Nosaukums | FPGA Design Automation: A Survey Grāmatas Foundations and Trends(r) in E 2. sējums. sējums Foundations and trends in electronic design automation, ISSN 1551-3947 |
| Autori | Deming Chen, Jason Cong, Peichan Pan |
| Izdevums: | jauns izdevums |
| Izdevējs | Now Publishers Inc, 2006 |
| ISBN | 1933019387, 9781933019383 |
| Apjoms | 140 lappuses |
| Eksportēt avotu | BiBTeX EndNote RefMan |