FPGA Design Automation: A Survey
FPGA Design Automation: A Survey is an up-to-date comprehensive survey/tutorial of FPGA design automation, with an emphasis on the recent developments within the past 5 to 10 years. The focus is on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow: routing and placement, circuit clustering, technology mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. FPGA Design Automation: A Survey can be used as both a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field.
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algorithm ASIC behavior synthesis CAPRI channel choice node clock tree COBRA-ABS computer-aided design Config SRAMs connected graph constraints CPLD critical paths datapath decomposition deﬁned delay design speciﬁcation detailed routing diﬀerent duplicate dynamic power eﬀective area estimated fanout count example fanin ﬁnal mapping solution ﬁnd ﬁxed FloorPlanner FPGA chips FPGA core FPGA global routing FPGA routing architecture function hierarchy high-current path high-level synthesis IMap implementation input iterative label layout Layout-driven logic blocks logic synthesis LUTs macrocell Manhattan distance mapping and clustering mapping graph metric space module instances nect netlist node represents optimization output p-terms partitioning placement Power gating architecture programmable programmable logic device replicate retiming router routing resource graph runtime selected set-covering short-circuit power signiﬁcant speciﬁcation languages standard cell designs standby Structural Mapping structural tree switch block switching activity switching power synthesis ﬂow techniques technology mapping tion topologies tree in 83 Verilog VHDL Xilinx
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