Logic Synthesis and VerificationSoha Hassoun, Tsutomu Sasao Springer Science & Business Media, 2012. gada 6. dec. - 454 lappuses Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc. |
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1.–5. rezultāts no 59.
. lappuse
... Technology Mapping Leon Stok and Vivek Tiwari 5.1 Introduction 5.2 Decomposition 5.3 Pattern Matching 5.4 Covering ix xi 1 1 2 12 21 29 29 31 40 50 60 61 65 65 67 71 84 89 89 90 91 96 98 101 104 110 111 115 115 117 120 121 132 137 5.5 ...
... Technology Mapping Leon Stok and Vivek Tiwari 5.1 Introduction 5.2 Decomposition 5.3 Pattern Matching 5.4 Covering ix xi 1 1 2 12 21 29 29 31 40 50 60 61 65 65 67 71 84 89 89 90 91 96 98 101 104 110 111 115 115 117 120 121 132 137 5.5 ...
. lappuse
... technology concerns . They include : technology mapping ( Chapter 5 ) , technology - based transformations ( Chapter 6 ) , log- ical and physical design flows ( Chapter 7 ) , and logic synthesis for low power ( Chapter 8 ) . Part III ...
... technology concerns . They include : technology mapping ( Chapter 5 ) , technology - based transformations ( Chapter 6 ) , log- ical and physical design flows ( Chapter 7 ) , and logic synthesis for low power ( Chapter 8 ) . Part III ...
31. lappuse
... technology mapping ) multi - level circuit structure . A Boolean network is a directed acyclic graph ( DAG ) . Nodes having no incom- ing edges , called primary input nodes , represent the primary inputs ( external inputs ) of a circuit ...
... technology mapping ) multi - level circuit structure . A Boolean network is a directed acyclic graph ( DAG ) . Nodes having no incom- ing edges , called primary input nodes , represent the primary inputs ( external inputs ) of a circuit ...
62. lappuse
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86. lappuse
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Saturs
29 | |
Chapter 3 | 64 |
Chapter 4 | 89 |
Chapter 5 | 115 |
Chapter 6 | 141 |
Chapter 7 | 166 |
Chapter 8 | 197 |
Chapter 9 | 225 |
Chapter 10 | 254 |
Chapter 11 | 285 |
Chapter 12 | 309 |
Chapter 13 | 342 |
Chapter 14 | 373 |
Chapter 15 | 403 |
Appendices | 435 |
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algebraic algorithm applied assignment asynchronous circuits ATPG backtrack binary binary decision diagrams Boolean function Brayton buffering capacitance cells chapter clause clock combinational Computer Science Computer-Aided Design Conf Conference on Computer-Aided constraints cost covering cube cutpoints decision diagrams decomposition delay model Design Automation Conference efficient encoding equivalence checking example false path fanin fanout finite state machines flexibility formal verification global graph hazard-free heuristic IEEE Trans IEEE Transactions implementation iterative latch literals load logic functions logic minimization logic optimization logic synthesis machine match methods minimum multi-level logic multiple-valued functions multiple-valued logic netlist node OBDD operation partition placement problem Proc propagation reachable reduced representation represented resizing retiming routing Sangiovanni-Vincentelli sequential shown in Figure signal solution specific SPFD static timing analysis structure switching techniques technology mapping tion transformations transition tree two-level variable verification VLSI wire