Logic Synthesis and VerificationSoha Hassoun, Tsutomu Sasao Springer Science & Business Media, 2012. gada 6. dec. - 454 lappuses Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc. |
No grāmatas satura
1.–5. rezultāts no 98.
v. lappuse
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... figures ( percents , medians , etc . ) .- Percents , medians , and means , as well as certain rates and ratios are shown in these reports . For all types of derived figures in this report , the figure is not presented ( but indicated by ...
8. lappuse
If the data shown in Figure 1 is reduced according to the inverse square function indicated in Equation 1 , on ... shown in Figures 2 and 3 . Figure 2 shows annealing factors versus time following a 1.8 x 10 ' NVT ( E > 0. 01 MeV ...
If the data shown in Figure 1 is reduced according to the inverse square function indicated in Equation 1 , on ... shown in Figures 2 and 3 . Figure 2 shows annealing factors versus time following a 1.8 x 10 ' NVT ( E > 0. 01 MeV ...
3. lappuse
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... shown in figure 2. Table 1 lists the salt beds and their depths and thicknesses as determined from the logs . The log data are supplemented by data from a or sample descriptions , also from Ohio Division of Geological Survey files ...
120. lappuse
... Fig. 5. Presynapsis stage of the primary spermatocyte. The chromosomes are in the form of threads and are sixteen in number, but not all are shown in the figure. Fig. 6. Commencement of synapsis. The chromosomes are denser than in the ...
... Fig. 5. Presynapsis stage of the primary spermatocyte. The chromosomes are in the form of threads and are sixteen in number, but not all are shown in the figure. Fig. 6. Commencement of synapsis. The chromosomes are denser than in the ...
12. lappuse
... shown in figure 5. The rate of heat transfer to the airfoil at a given Mach number decreases rapidly as the altitude ... figure 3 is equal to H / S in figure 5. This equilibrium surface temperature is shown in figure 6 as a function of ...
... shown in figure 5. The rate of heat transfer to the airfoil at a given Mach number decreases rapidly as the altitude ... figure 3 is equal to H / S in figure 5. This equilibrium surface temperature is shown in figure 6 as a function of ...
Saturs
29 | |
Chapter 3 | 64 |
Chapter 4 | 89 |
Chapter 5 | 115 |
Chapter 6 | 141 |
Chapter 7 | 166 |
Chapter 8 | 197 |
Chapter 9 | 225 |
Chapter 10 | 254 |
Chapter 11 | 285 |
Chapter 12 | 309 |
Chapter 13 | 342 |
Chapter 14 | 373 |
Chapter 15 | 403 |
Appendices | 435 |
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algebraic algorithm applied assignment asynchronous circuits ATPG backtrack binary binary decision diagrams Boolean function Brayton buffering capacitance cells chapter clause clock combinational Computer Science Computer-Aided Design Conf Conference on Computer-Aided constraints cost covering cube cutpoints decision diagrams decomposition delay model Design Automation Conference efficient encoding equivalence checking example false path fanin fanout finite state machines flexibility formal verification global graph hazard-free heuristic IEEE Trans IEEE Transactions implementation iterative latch literals load logic functions logic minimization logic optimization logic synthesis machine match methods minimum multi-level logic multiple-valued functions multiple-valued logic netlist node OBDD operation partition placement problem Proc propagation reachable reduced representation represented resizing retiming routing Sangiovanni-Vincentelli sequential shown in Figure signal solution specific SPFD static timing analysis structure switching techniques technology mapping tion transformations transition tree two-level variable verification VLSI wire