Logic Synthesis and VerificationSoha Hassoun, Tsutomu Sasao Springer Science & Business Media, 2012. gada 6. dec. - 454 lappuses Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc. |
No grāmatas satura
1.5. rezultāts no 88.
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Soha Hassoun, Tsutomu Sasao. 94 LOGIC SYNTHESIS AND VERIFICATION λι λ = ? S δι 91- F 93 Fo x D λε gl g2 g4 96 g3 D 8 , P = ? edited by Soha Hassoun and Tsutomu Sasao consulting editor Robert K. Brayton Springer Science + Business Media ...
Soha Hassoun, Tsutomu Sasao. 94 LOGIC SYNTHESIS AND VERIFICATION λι λ = ? S δι 91- F 93 Fo x D λε gl g2 g4 96 g3 D 8 , P = ? edited by Soha Hassoun and Tsutomu Sasao consulting editor Robert K. Brayton Springer Science + Business Media ...
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... Logic Transformations Trends 141 141 143 144 160 Chapter 7 Logical and Physical Design : A flow Perspective Olivier Coudert 167 7.1 Introduction 167 7.2 Logical and Physical Design Challenges 168 7.3 ... LOGIC SYNTHESIS AND VERIFICATION.
... Logic Transformations Trends 141 141 143 144 160 Chapter 7 Logical and Physical Design : A flow Perspective Olivier Coudert 167 7.1 Introduction 167 7.2 Logical and Physical Design Challenges 168 7.3 ... LOGIC SYNTHESIS AND VERIFICATION.
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... Logic Synthesis and Verification 403 Robert K. Brayton 15.1 Logic Synthesis - Introduction 403 15.2 Techniques On The Edge 404 15.3 Physical / Logical Design 413 15.4 DSM Issues 416 15.5 Design For Low Power 420 15.6 Use In Software ...
... Logic Synthesis and Verification 403 Robert K. Brayton 15.1 Logic Synthesis - Introduction 403 15.2 Techniques On The Edge 404 15.3 Physical / Logical Design 413 15.4 DSM Issues 416 15.5 Design For Low Power 420 15.6 Use In Software ...
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Soha Hassoun, Tsutomu Sasao. Foreword There is no question that logic synthesis has had an unprecedented impact on the design of state - of - the - art integrated circuits ever since its inception . At the very first ... logic synthesis and.
Soha Hassoun, Tsutomu Sasao. Foreword There is no question that logic synthesis has had an unprecedented impact on the design of state - of - the - art integrated circuits ever since its inception . At the very first ... logic synthesis and.
. lappuse
... logic synthesis and verifica- tion . It consists of fifteen chapters , each focusing on a distinct aspect . Each chapter presents key developments , outlines future challenges , and lists essen- tial references . Two unique features of ...
... logic synthesis and verifica- tion . It consists of fifteen chapters , each focusing on a distinct aspect . Each chapter presents key developments , outlines future challenges , and lists essen- tial references . Two unique features of ...
Saturs
29 | |
Chapter 3 | 64 |
Chapter 4 | 89 |
Chapter 5 | 115 |
Chapter 6 | 141 |
Chapter 7 | 166 |
Chapter 8 | 197 |
Chapter 9 | 225 |
Chapter 10 | 254 |
Chapter 11 | 285 |
Chapter 12 | 309 |
Chapter 13 | 342 |
Chapter 14 | 373 |
Chapter 15 | 403 |
Appendices | 435 |
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algebraic algorithm applied assignment asynchronous circuits ATPG backtrack binary binary decision diagrams Boolean function Brayton buffering capacitance cells chapter clause clock combinational Computer Science Computer-Aided Design Conf Conference on Computer-Aided constraints cost covering cube cutpoints decision diagrams decomposition delay model Design Automation Conference efficient encoding equivalence checking example false path fanin fanout finite state machines flexibility formal verification global graph hazard-free heuristic IEEE Trans IEEE Transactions implementation iterative latch literals load logic functions logic minimization logic optimization logic synthesis machine match methods minimum multi-level logic multiple-valued functions multiple-valued logic netlist node OBDD operation partition placement problem Proc propagation reachable reduced representation represented resizing retiming routing Sangiovanni-Vincentelli sequential shown in Figure signal solution specific SPFD static timing analysis structure switching techniques technology mapping tion transformations transition tree two-level variable verification VLSI wire