Logic Synthesis and Verification
Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges.
Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.
Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field.
Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools.
From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.
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MultiLevel Logic Optimization
Soha Hassoum and Tiziano Villa
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ACM/IEEE algebraic algorithm applied arrival asynchronous asynchronous circuits ATPG backtrack search Berkelaar binary binary decision diagrams Boolean function buffering capacitance chapter clause clock combinational Computer Science Computer-Aided Design Conf Conference on Computer-Aided constraints cube cutpoints decision diagrams decomposition delay model Design Automation Conference edge efficient encoding equivalence checking example false path fanins fanout finite state machines flexibility formal verification gate graph heuristic IEEE Trans IEEE Transactions implementation implication iterative latch literals logic functions logic minimization logic optimization logic synthesis machine match methods minimum multi-level logic multiple-valued functions multiple-valued logic netlist node OBDD operations partition placement primary inputs problem Proc propagation reachable register correspondence representation represented retiming Sangiovanni-Vincentelli Section shown in Figure signal specific SPFD static timing analysis structure switching techniques technology mapping tion transition tree two-level variable verification vertex VLSI wire