Fine- and Coarse-Grain Reconfigurable ComputingStamatis Vassiliadis, Dimitrios Soudris Springer Science & Business Media, 2007. gada 24. sept. - 381 lappuses Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures: The FPGA technology is defined, which includes architecture, logic block structure, interconnect, and configuration methods and existing fine-grain reconfigurable architectures emerged from both academia and industry. Additionally, the implementation techniques and CAD tools developed to facilitate the implementation of a system in reconfigurable hardware by the industry and academia are provided. In addition the features, the advantages and limitations of the coarse-grain reconfigurable systems, the specific issues that should be addressed during the design phase, as well as representative existing coarse-grain reconfigurable systems are explained. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES&DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors. |
No grāmatas satura
... Systems Application Domain-Specific System Application Specific Integrated Circuits Application – Specific Integrated Processor Custom Configured Unit Control Data Flow Graphs Coarse-Grain Reconfigurable Units ... Functional Unit Reduced ...
... functional unit (RFU) into the pipeline of an aggressive, dynamically-scheduled superscalar processor. The RFU is a small and fast field-programmable gate arraylike device that can implement application specific operations. The Chimaera ...
... functional unit, 3 multiplexers for the outputs, and tri-state drivers for the segmented channels. In Triptych, the functional unit is a 3-input LUT, with an optional D-latch on its output. 1.3.2.4 UTFPGA1 The work at the University of ...
... functional unit. A dynamically reconfigurable FPGA must provide means of communicating intermediate results between different configuration instantiations. The proposed RLB_Bus RLB Layer Routing Layer Fig. 1.15 Block diagram of the 3-D ...
... functional unit FPGA allows direct communication between any two configuration instantiations. The SaveState register is provided in order to allow the present state to be saved for subsequent processing. The current state can be loaded ...
Saturs
3 | |
A Survey of CoarseGrain Reconfigurable Architectures and | 60 |
Amdrel | 153 |
A CoarseGrain Dynamically Reconfigurable System | 181 |
Polymorphic Instruction Set Computers | 216 |
Architecture and Compiler for CoarseGrain | 255 |
A Taxonomy of FieldProgrammable Custom Computing Machines | 299 |
Index | 379 |
Citi izdevumi - Skatīt visu
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Ierobežota priekšskatīšana - 2007 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2008 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2014 |