Fine- and Coarse-Grain Reconfigurable ComputingStamatis Vassiliadis, Dimitrios Soudris Springer Science & Business Media, 2007. gada 24. sept. - 381 lappuses Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures: The FPGA technology is defined, which includes architecture, logic block structure, interconnect, and configuration methods and existing fine-grain reconfigurable architectures emerged from both academia and industry. Additionally, the implementation techniques and CAD tools developed to facilitate the implementation of a system in reconfigurable hardware by the industry and academia are provided. In addition the features, the advantages and limitations of the coarse-grain reconfigurable systems, the specific issues that should be addressed during the design phase, as well as representative existing coarse-grain reconfigurable systems are explained. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES&DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors. |
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1.–5. rezultāts no 54.
... optimized circuits that are loaded and unloaded dynamically during the operation of the system. Dynamic reconfiguration is based on the concept of virtual hardware, which is similar to the idea of virtual memory. In this case, the ...
... optimized for such operations. 1.3.1.4 Pleiades The Pleiades processor [28] combines an on-chip microprocessor with an array of heterogeneous programmable computational units of different granularities, which are called satellite ...
... optimization (for speed), and little time was spent on layout optimization. This was a first attempt that provided some insight into the problems faced in the design and layout of an FPGA. The general architecture of UTFPGA1 is shown in ...
... Channel I I One tile I I I/O Pad I/O Pad I/O Pad I/O Pad I/O Pad optimizing for delay can be achieved by having some hardwired. Fig. 1.13 General architecture of UTFPGA1 Fig. 1.17 Spartan – 3 CLB organization. 22 K. Tatas et al.
Stamatis Vassiliadis, Dimitrios Soudris. optimizing for delay can be achieved by having some hardwired connections between ... optimization issues concurrently. A hybrid interconnect structure incorporating Nearest Neighbor Connections ...
Saturs
3 | |
A Survey of CoarseGrain Reconfigurable Architectures and | 60 |
Amdrel | 153 |
A CoarseGrain Dynamically Reconfigurable System | 181 |
Polymorphic Instruction Set Computers | 216 |
Architecture and Compiler for CoarseGrain | 255 |
A Taxonomy of FieldProgrammable Custom Computing Machines | 299 |
Index | 379 |
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Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Ierobežota priekšskatīšana - 2007 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2008 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2014 |