Fine- and Coarse-Grain Reconfigurable Computing
Stamatis Vassiliadis, Dimitrios Soudris
Springer Science & Business Media, 2007. gada 24. sept. - 381 lappuses
Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described.
Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures:
The FPGA technology is defined, which includes architecture, logic block structure, interconnect, and configuration methods and existing fine-grain reconfigurable architectures emerged from both academia and industry. Additionally, the implementation techniques and CAD tools developed to facilitate the implementation of a system in reconfigurable hardware by the industry and academia are provided.
In addition the features, the advantages and limitations of the coarse-grain reconfigurable systems, the specific issues that should be addressed during the design phase, as well as representative existing coarse-grain reconfigurable systems are explained.
In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES&DRESC, and, a new classification according to microcoded architectural criteria are described.
Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors.
1.5. rezultāts no 5.
All FPGAs are composed of three fundamental components: logic blocks, I/O
blocks and programmable routing. A circuit is implemented in an FPGA by
programming each logic block to implement a small portion of the logic required
by the ...
The configurable logic block (CLB) , is responsible for implementing the
gatelevel functionality required for each application. The logic block is defined by
its internal structure and granularity. The structure defines the different kinds of
Garp's reconfigurable array is composed of entities called blocks. One block on
each row is known as a control block. The rest of the blocks in the array are logic
blocks, which correspond roughly to the CLBs of the Xilinx 4000 series. The Garp
optimizing for delay can be achieved by having some hardwired connections
between logic blocks. The block also contains a resettable D flip-flop. The routing
architecture has tracks segmented into lengths of one, two, and three tiles.
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