Fine- and Coarse-Grain Reconfigurable ComputingStamatis Vassiliadis, Dimitrios Soudris Springer Science & Business Media, 2007. gada 24. sept. - 381 lappuses Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures: The FPGA technology is defined, which includes architecture, logic block structure, interconnect, and configuration methods and existing fine-grain reconfigurable architectures emerged from both academia and industry. Additionally, the implementation techniques and CAD tools developed to facilitate the implementation of a system in reconfigurable hardware by the industry and academia are provided. In addition the features, the advantages and limitations of the coarse-grain reconfigurable systems, the specific issues that should be addressed during the design phase, as well as representative existing coarse-grain reconfigurable systems are explained. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES&DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors. |
No grāmatas satura
1.–5. rezultāts no 84.
... configuration information, and comes in different flavors. It has a strong impact on the area and performance of the array. The main programming technologies are: Static Random Access Memory (SRAM) [1], antifuse [2], and non-volatile ...
... memory cells, the area of the FPGA is dominated by configuration storage. The SRAM method of programming offers the convenience of reusing a single device for implementing different applications by loading different configurations. This ...
... configuration. Many of the existing reconfigurable systems are statically ... memory. In this case, the physical hardware is much smaller than the sum of ... configuration each time and can be programmed using a serial stream of ...
... memory bits for each programming bit location [18]. These memory bits can be thought of as multiple planes of configuration information, each of which can be active at a given moment, but the device can quickly switch between different ...
... memory latency by taking advantage of two types of locality, spatial and temporal locality. These two localities also apply to the caching of configurations on the FPGA in coupled processor-FPGA systems. The challenge in configuration ...
Saturs
3 | |
A Survey of CoarseGrain Reconfigurable Architectures and | 60 |
Amdrel | 153 |
A CoarseGrain Dynamically Reconfigurable System | 181 |
Polymorphic Instruction Set Computers | 216 |
Architecture and Compiler for CoarseGrain | 255 |
A Taxonomy of FieldProgrammable Custom Computing Machines | 299 |
Index | 379 |
Citi izdevumi - Skatīt visu
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Ierobežota priekšskatīšana - 2007 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2008 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2014 |