Fine- and Coarse-Grain Reconfigurable ComputingStamatis Vassiliadis, Dimitrios Soudris Springer Science & Business Media, 2007. gada 24. sept. - 381 lappuses Fine- and Coarse-Grain Reconfigurable Computing gives the basic concepts and building blocks for the design of Fine- (or FPGA) and Coarse-Grain Reconfigurable Architectures. Recently-developed integrated architecture design and software-supported design flow of FPGA and coarse-grain reconfigurable architecture are also described. Part I consists of two extensive surveys of FPGA and Coarse-Grain Reconfigurable Architectures: The FPGA technology is defined, which includes architecture, logic block structure, interconnect, and configuration methods and existing fine-grain reconfigurable architectures emerged from both academia and industry. Additionally, the implementation techniques and CAD tools developed to facilitate the implementation of a system in reconfigurable hardware by the industry and academia are provided. In addition the features, the advantages and limitations of the coarse-grain reconfigurable systems, the specific issues that should be addressed during the design phase, as well as representative existing coarse-grain reconfigurable systems are explained. In Part II, case studies, innovative research results about reconfigurable architectures and design frameworks from three projects AMDREL, MOLEN and ADRES&DRESC, and, a new classification according to microcoded architectural criteria are described. Fine- and Coarse-Grain Reconfigurable Computing is an essential reference for researchers and professionals and can be used as a textbook by undergraduate, graduate students and professors. |
No grāmatas satura
1.5. rezultāts no 32.
... clusters. These clusters are recursively connected to form a hierarchical structure. Figure 1.6 illustrates a possible architecture. The speed of the network is determined by the number of routing switches it has to pass through. The ...
... cluster. The number of inputs to the cluster for use as inputs by the LUTs. The number of clock inputs to a cluster (for use by the registers). The advantage of using a k-input LUT (k-LUT) is that it can realize any combinational ...
... clusters with 4-inputs LUT instead of one 4-input LUT, results in an area decrease of 10% [11]. 1.2.3. Programming. Technology. As already mentioned, the logic and routing resources of an FPGA are uncommitted, and must be programmed ...
... cluster of 3-input LUTs. This clustering technique makes it possible to combine the results of the four 3-input LUTs in various ways to simultaneously realize up to three different functions in a logic block. The combination of the ...
... clusters. A cluster is formed by a square array of RLBs. The size of the cluster will be determined in Section V-B. Each cluster is associated with a cluster memory block and a switch box in the routing layer. The cluster memory block ...
Saturs
3 | |
A Survey of CoarseGrain Reconfigurable Architectures and | 60 |
Amdrel | 153 |
A CoarseGrain Dynamically Reconfigurable System | 181 |
Polymorphic Instruction Set Computers | 216 |
Architecture and Compiler for CoarseGrain | 255 |
A Taxonomy of FieldProgrammable Custom Computing Machines | 299 |
Index | 379 |
Citi izdevumi - Skatīt visu
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Ierobežota priekšskatīšana - 2007 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2008 |
Fine- and Coarse-Grain Reconfigurable Computing Stamatis Vassiliadis,Dimitrios Soudris Priekšskatījums nav pieejams - 2014 |