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" M. Wan, H. Zhang, V. George, M. Benes, A. Abnous, V. Prabhu, and J. Rabaey. "Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System". "
Building ASIPs: The Mescal Methodology - 340. lappuse
autors: Matthias Gries, Kurt Keutzer - 2005 - 350 lapas
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Programmable Digital Signal Processors: Architecture: Programming, and ...

Yu Hen Hu - 2001 - 456 lapas
...submicron. Proceedings, 1nternational Conference on Computer-Aided Design. 1998. pp 203-211. 1 16. M Wan. H Zhang. V George. M Benes, A Abnous. V Prabhu. J Rabaey. Design methodology of a low-energy reconfigurable single-chip DSP system. VLS1 Signal Process...
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Fine- and Coarse-Grain Reconfigurable Computing

Stamatis Vassiliadis, Dimitrios Soudris - 2007 - 381 lapas
...on VLSI Signal Processing, pp. 461^170, 1996. 19. M. Wan, H. Zhang, V. George, M. Benes, A. Arnous, V. Prabhu, and J. Rabaey, "Design Methodology of a...Low-Energy Reconfigurable Single-Chip DSP System", in Journal of VLSI Signal Processing, vol. 28, no. 1-2, pp. 47-61, May-June 2001. 20. K. Compton, and...
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